From patchwork Thu Apr 10 09:55:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 28147 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qg0-f71.google.com (mail-qg0-f71.google.com [209.85.192.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 95AB820671 for ; Thu, 10 Apr 2014 09:56:10 +0000 (UTC) Received: by mail-qg0-f71.google.com with SMTP id j5sf6948753qga.2 for ; Thu, 10 Apr 2014 02:56:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=hSZFYpyi9rxu18h46W7q9CZo95a2sBebK5QYpP+EfJI=; b=YN2ijazGBlMmFyDyQhc07LF4zNSzHkj1jwo4j0hYjj0ZssVsDWb61bJfLUkDytGrXw VDVbLcbFBcqv6xETrMQKLoVvxltAWWsSh8w5T/K5LWOLbjbjAmdSxkZtvK4v9ZGVPz6I pXcHbQSMoJhle/fVv8YKG/LyXwEoDMAXLg05bxErG1ei9rfEyIKzmzn0br32Wp/OegT8 qKD0UCNVt/BX9w6AROiRHIRFAwW2KE+L8kXcrEWwT4sSEGiW1Ci6HIzi3giC5NWpXfob ZovJg7p90/5dgQbhplL6JtyyKIpQthUA8f1fyAW2a92XzsDc/TicYLwetTmE2trmqIdz 4JqQ== X-Gm-Message-State: ALoCoQnc9I++Al++4a5pn9LGQJzjwR0RjVGBkWMI5CpJlJzzioIIQ0wiafN5e0b/UwK7E0dbEbMM X-Received: by 10.236.142.212 with SMTP id i60mr6055556yhj.39.1397123770351; Thu, 10 Apr 2014 02:56:10 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.26.183 with SMTP id 52ls1102797qgv.38.gmail; Thu, 10 Apr 2014 02:56:10 -0700 (PDT) X-Received: by 10.52.6.162 with SMTP id c2mr11462475vda.6.1397123770197; Thu, 10 Apr 2014 02:56:10 -0700 (PDT) Received: from mail-vc0-f172.google.com (mail-vc0-f172.google.com [209.85.220.172]) by mx.google.com with ESMTPS id cb3si608771vdc.41.2014.04.10.02.56.10 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 10 Apr 2014 02:56:10 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.220.172; Received: by mail-vc0-f172.google.com with SMTP id la4so3259580vcb.31 for ; Thu, 10 Apr 2014 02:56:10 -0700 (PDT) X-Received: by 10.221.26.10 with SMTP id rk10mr13780863vcb.0.1397123770102; Thu, 10 Apr 2014 02:56:10 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp45055vcb; Thu, 10 Apr 2014 02:56:09 -0700 (PDT) X-Received: by 10.68.133.163 with SMTP id pd3mr18395741pbb.166.1397123769417; Thu, 10 Apr 2014 02:56:09 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id xe4si1873677pbc.456.2014.04.10.02.56.08; Thu, 10 Apr 2014 02:56:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965640AbaDJJ4H (ORCPT + 9 others); Thu, 10 Apr 2014 05:56:07 -0400 Received: from mail-wi0-f182.google.com ([209.85.212.182]:51764 "EHLO mail-wi0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965541AbaDJJzz (ORCPT ); Thu, 10 Apr 2014 05:55:55 -0400 Received: by mail-wi0-f182.google.com with SMTP id d1so4673642wiv.15 for ; Thu, 10 Apr 2014 02:55:54 -0700 (PDT) X-Received: by 10.180.207.10 with SMTP id ls10mr41841467wic.22.1397123754486; Thu, 10 Apr 2014 02:55:54 -0700 (PDT) Received: from localhost.localdomain (AToulouse-654-1-377-242.w86-199.abo.wanadoo.fr. [86.199.232.242]) by mx.google.com with ESMTPSA id hu7sm15690125wib.10.2014.04.10.02.55.53 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 10 Apr 2014 02:55:53 -0700 (PDT) From: Daniel Lezcano To: kgene.kim@samsung.com Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, t.figa@samsung.com, linaro-kernel@lists.linaro.org, b.zolnierkie@samsung.com, sachin.kamat@linaro.org, viresh.kumar@linaro.org, rjw@rjwysocki.net Subject: [PATCH V4 15/20] ARM: exynos: cpuidle: Move the AFTR state function into pm.c Date: Thu, 10 Apr 2014 11:55:46 +0200 Message-Id: <1397123751-1957-16-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1397123751-1957-1-git-send-email-daniel.lezcano@linaro.org> References: <1397123751-1957-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: daniel.lezcano@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , In order to remove depedency on pm code, let's move the 'exynos_enter_aftr' function into the pm.c file as well as the other helper functions. Signed-off-by: Daniel Lezcano --- arch/arm/mach-exynos/common.h | 1 + arch/arm/mach-exynos/cpuidle.c | 29 ----------------------------- arch/arm/mach-exynos/pm.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 30 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 9ef3f83..30123a0 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -62,5 +62,6 @@ struct exynos_pmu_conf { }; extern void exynos_sys_powerdown_conf(enum sys_powerdown mode); +extern void exynos_enter_aftr(void); #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */ diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index 0d3c839..5c5a4d1 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c @@ -30,35 +30,6 @@ #include "common.h" #include "regs-pmu.h" -#define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ - S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ - (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0)) -#define REG_DIRECTGO_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ - S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ - (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1)) - -#define S5P_CHECK_AFTR 0xFCBA0D10 - -/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ -static void exynos_set_wakeupmask(long mask) -{ - __raw_writel(mask, S5P_WAKEUP_MASK); -} - -static void exynos_cpu_set_boot_vector(long flags) -{ - __raw_writel(virt_to_phys(exynos_cpu_resume), REG_DIRECTGO_ADDR); - __raw_writel(flags, REG_DIRECTGO_FLAG); -} - -static void exynos_enter_aftr(void) -{ - exynos_set_wakeupmask(0x0000ff3e); - exynos_cpu_set_boot_vector(S5P_CHECK_AFTR); - /* Set value of power down register for aftr mode */ - exynos_sys_powerdown_conf(SYS_AFTR); -} - static int idle_finisher(unsigned long flags) { exynos_enter_aftr(); diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index c4138bf..f75d9b9 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -101,6 +101,35 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) return -ENOENT; } +#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ + S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ + (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0)) +#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \ + S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ + (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1)) + +#define S5P_CHECK_AFTR 0xFCBA0D10 + +/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ +static void exynos_set_wakeupmask(long mask) +{ + __raw_writel(mask, S5P_WAKEUP_MASK); +} + +static void exynos_cpu_set_boot_vector(long flags) +{ + __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR); + __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG); +} + +void exynos_enter_aftr(void) +{ + exynos_set_wakeupmask(0x0000ff3e); + exynos_cpu_set_boot_vector(S5P_CHECK_AFTR); + /* Set value of power down register for aftr mode */ + exynos_sys_powerdown_conf(SYS_AFTR); +} + /* For Cortex-A9 Diagnostic and Power control register */ static unsigned int save_arm_register[2];