| Message ID | 20201002122243.26849-8-l.stelmach@samsung.com |
|---|---|
| State | New |
| Headers | show |
| Series | Some fixes for spi-s3c64xx | expand |
On Fri, Oct 02, 2020 at 02:22:41PM +0200, Łukasz Stelmach wrote: > Make sure the cur_speed value used in s3c64xx_enable_datapath() > to configure DMA channel and in s3c64xx_wait_for_*() to calculate the > transfer timeout is set to the actual value of (half) the clock speed. > > Don't change non-CMU case, because no frequency calculation errors have > been reported. > > Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> > Suggested-by: Tomasz Figa <tomasz.figa@gmail.com> > Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com> For the future, tags are added in chronological order, so first is suggested (as someone suggested to make a patch), then your SoB (as you wrote it) and then my review (because you had to write a patch before I could review). All other patches here have these mixed up. No need to resend, but keep it in mind for the future. Best regards, Krzysztof
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index f85f40fd608c..0bd3e230350c 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -626,6 +626,7 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); if (ret) return ret; + sdd->cur_speed = clk_get_rate(sdd->src_clk) / 2; } else { /* Configure Clock */ val = readl(regs + S3C64XX_SPI_CLK_CFG);