| Message ID | 20201020171221.730-3-dmurphy@ti.com |
|---|---|
| State | New |
| Headers | show |
| Series | DP83TD510 Single Pair 10Mbps Ethernet PHY | expand |
> + ti,master-slave-mode: > + $ref: /schemas/types.yaml#definitions/uint32 > + default: 0 > + description: | > + Force the PHY to be configured to a specific mode. > + Force Auto Negotiation - 0 > + Force Master mode at 1v p2p - 1 > + Force Master mode at 2.4v p2p - 2 > + Force Slave mode at 1v p2p - 3 > + Force Slave mode at 2.4v p2p - 4 > + enum: [ 0, 1, 2, 3, 4 ] Is this a board hardware property? The fact value 0 means auto-neg suggests not. We already have ethtool configuration of master/slave for T1 PHYs: ommit bdbdac7649fac05f88c9f7ab18121a17fb591687 Author: Oleksij Rempel <linux@rempel-privat.de> Date: Tue May 5 08:35:05 2020 +0200 ethtool: provide UAPI for PHY master/slave configuration. This UAPI is needed for BroadR-Reach 100BASE-T1 devices. Due to lack of auto-negotiation support, we needed to be able to configure the MASTER-SLAVE role of the port manually or from an application in user space. Please can you look at using that UAPI. I assume that 1v p2p is the voltage of the signal put onto the twisted pair? I know the Marvell 1000BaseT PHYs allow this to be configured as well, but just downwards to save power. Maybe a PHY tunable would be better? Humm. Are 1v and 2.4v advertised so it can be auto negotiated? Maybe a PHY tunable is not correct? Is this voltage selection actually more like pause and EEE? Andrew
> Humm. Are 1v and 2.4v advertised so it can be auto negotiated? Maybe a > PHY tunable is not correct? Is this voltage selection actually more > like pause and EEE? [Goes and looks at the datasheet] Register 0x20E, bit 13: 1 = Advertise that the 10BASE-T1L PHY has increased transmit/ receive level ability 0 = Do not advertise that the 10BASE-T1L PHY has increased transmit/receive level ability (default) So does this mean 2.4v? Andrew
Andrew On 10/20/20 2:07 PM, Andrew Lunn wrote: >> Humm. Are 1v and 2.4v advertised so it can be auto negotiated? Maybe a >> PHY tunable is not correct? Is this voltage selection actually more >> like pause and EEE? > [Goes and looks at the datasheet] > > Register 0x20E, bit 13: > > 1 = Advertise that the 10BASE-T1L PHY has increased transmit/ > receive level ability > 0 = Do not advertise that the 10BASE-T1L PHY has increased > transmit/receive level ability (default) > > So does this mean 2.4v? This can also be strapped to a certain voltage level. The device may not have the regulators on board to drive a 2.4v signal. 1v signal AVDD is 1.8v and 2.4v the AVDD needs to be at least 3.3v This Strap defines the voltage level requested by PHY during auto negotiation. It is reflected in bit 12 of 0x20E. While using Force mode for Linkup, the strap controls the output voltage and reflects in bit 12 of 0x18F6 Bit 12 1 = Enable 2.4 Vpp operating mode 0 = Enable 1.0 Vpp operating mode So maybe this is a hybrid of tunable for master/slave and a DT for voltage level since the ability of the board to drive the signal can vary. Dan > Andrew
diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml new file mode 100644 index 000000000000..171aed0f2503 --- /dev/null +++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI DP83TD510 ethernet PHY + +allOf: + - $ref: "ethernet-controller.yaml#" + - $ref: "ethernet-phy.yaml#" + +maintainers: + - Dan Murphy <dmurphy@ti.com> + +description: | + The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and + RGMII interfaces. + + Specifications about the Ethernet PHY can be found at: + http://www.ti.com/lit/ds/symlink/dp83td510e.pdf + +properties: + reg: + maxItems: 1 + + tx-fifo-depth: + description: | + Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble + depths. The valid nibble depths are 4, 5, 6 and 8. + default: 5 + + rx-internal-delay-ps: + description: | + Setting this property to a non-zero number sets the RX internal delay + for the PHY. The internal delay for the PHY is fixed to 30ns relative + to receive data. + + tx-internal-delay-ps: + description: | + Setting this property to a non-zero number sets the TX internal delay + for the PHY. The internal delay for the PHY has a range of -4 to 4ns + relative to transmit data. + + ti,master-slave-mode: + $ref: /schemas/types.yaml#definitions/uint32 + default: 0 + description: | + Force the PHY to be configured to a specific mode. + Force Auto Negotiation - 0 + Force Master mode at 1v p2p - 1 + Force Master mode at 2.4v p2p - 2 + Force Slave mode at 1v p2p - 3 + Force Slave mode at 2.4v p2p - 4 + enum: [ 0, 1, 2, 3, 4 ] + +required: + - reg + +examples: + - | + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + ethphy0: ethernet-phy@0 { + reg = <0>; + tx-fifo-depth = <5>; + rx-internal-delay-ps = <1>; + tx-internal-delay-ps = <1>; + }; + };
The DP83TD510 is a 10M single twisted pair Ethernet PHY Signed-off-by: Dan Murphy <dmurphy@ti.com> --- .../devicetree/bindings/net/ti,dp83td510.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml