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[209.132.180.67]) by mx.google.com with ESMTP id ll8si13065062pab.192.2014.05.13.04.58.29; Tue, 13 May 2014 04:58:29 -0700 (PDT) Received-SPF: none (google.com: linux-samsung-soc-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932385AbaEML62 (ORCPT + 9 others); Tue, 13 May 2014 07:58:28 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:13545 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932609AbaEML61 (ORCPT ); Tue, 13 May 2014 07:58:27 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N5I008R7H9DAJC0@mailout1.samsung.com> for linux-samsung-soc@vger.kernel.org; Tue, 13 May 2014 20:58:26 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.124]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id E6.5F.09952.1E802735; Tue, 13 May 2014 20:58:25 +0900 (KST) X-AuditID: cbfee690-b7fcd6d0000026e0-24-537208e1926f Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 5F.69.27725.1E802735; Tue, 13 May 2014 20:58:25 +0900 (KST) Received: from abhilash-ubuntu.sisodomain.com ([107.108.73.92]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N5I00EZ6H7CR340@mmp1.samsung.com>; Tue, 13 May 2014 20:58:25 +0900 (KST) From: Abhilash Kesavan To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, abrestic@chromium.org, thomas.ab@samsung.com, inderpal.s@samsung.com, lorenzo.pieralisi@arm.com, nicolas.pitre@linaro.org, Dave.Martin@arm.com, t.figa@samsung.com Cc: kesavan.abhilash@gmail.com, Leela Krishna Amudala , Abhilash Kesavan Subject: [PATCH v6 1/5] ARM: EXYNOS: Add generic cpu power control functions for all exynos based SoCs Date: Tue, 13 May 2014 17:28:40 +0530 Message-id: <1399982324-27879-2-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1399982324-27879-1-git-send-email-a.kesavan@samsung.com> References: <1399982324-27879-1-git-send-email-a.kesavan@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprNIsWRmVeSWpSXmKPExsWyRsSkRvchR1GwwerNphaP1yxmslj5/i+j RdPcPYwWu+99YbRY81fJonfBVTaLCfs/sFhsenyN1WLG+X1MFm9+v2C3+PTsH7vF+hmvWSw6 ljE68HqsmbeG0WN2w0UWj52z7rJ73Lm2h81j85J6j74tqxg9Pm+SC2CP4rJJSc3JLEst0rdL 4Mo4//ckY8Eq8YpNT+axNTAeFe5i5OSQEDCRmHvxNTOELSZx4d56ti5GLg4hgaWMEjNf3GeB Kbq5cy4LRGIRo8S6Jb+gqvqYJLqPv2QHqWIT0JNY8O8rM0hCRKCHSWLtnhawdmaBOomdc/vA dggLZEjsun0ELM4ioCpx9f0dMJtXwFXi364tQDUcQOsUJOZMsgEJcwq4SUxrbQVrFQIquXGu kQniokvsErdW60KMEZD4NvkQC0SrrMSmA1DfSEocXHGDZQKj8AJGhlWMoqkFyQXFSelFJnrF ibnFpXnpesn5uZsYgRFz+t+zCTsY7x2wPsSYDDRuIrOUaHI+MOLySuINjc2MLExNTI2NzC3N SBNWEudVe5QUJCSQnliSmp2aWpBaFF9UmpNafIiRiYNTqoGRf27UvrXlhSb3Wkv2MpfJP15X OV9ov9vvD9P4Pm3YIj4xdNbeU5PfHJsUcLmA2eoKi3Cny7a7822NFkwKXhOt8+ivFSuL366i tLWcJ9Nbv5ZvvWe5Ly/Ksoz3qHeEc3zauo5zZzYeiXy/7v89e63W1Qs/hDZ51J56zC7AvrUz O3WPF6OqxpVqJZbijERDLeai4kQA776NUa4CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrJIsWRmVeSWpSXmKPExsVy+t9jAd2HHEXBBmvP6lo8XrOYyWLl+7+M Fk1z9zBa7L73hdFizV8li94FV9ksJuz/wGKx6fE1VosZ5/cxWbz5/YLd4tOzf+wW62e8ZrHo WMbowOuxZt4aRo/ZDRdZPHbOusvucefaHjaPzUvqPfq2rGL0+LxJLoA9qoHRJiM1MSW1SCE1 Lzk/JTMv3VbJOzjeOd7UzMBQ19DSwlxJIS8xN9VWycUnQNctMwfoWCWFssScUqBQQGJxsZK+ HaYJoSFuuhYwjRG6viFBcD1GBmggYQ1jxvm/JxkLVolXbHoyj62B8ahwFyMnh4SAicTNnXNZ IGwxiQv31rN1MXJxCAksYpRYt+QXlNPHJNF9/CU7SBWbgJ7Egn9fmUESIgI9TBJr97SAtTML 1EnsnNvHDGILC2RI7Lp9BCzOIqAqcfX9HTCbV8BV4t+uLUA1HEDrFCTmTLIBCXMKuElMa20F axUCKrlxrpFpAiPvAkaGVYyiqQXJBcVJ6bmGesWJucWleel6yfm5mxjBEflMagfjygaLQ4wC HIxKPLw/jQuDhVgTy4orcw8xSnAwK4nwun8CCvGmJFZWpRblxxeV5qQWH2JMBjpqIrOUaHI+ MFnklcQbGpuYmxqbWppYmJhZkiasJM57oNU6UEggPbEkNTs1tSC1CGYLEwenVAOjwpn5Zi/W uNtMNmn86HH66T/2f9ctOUutvzAeNZF/9ia//Mi0lnlh+09H7vW8ZvhTxfRbSq7eHrP0hSZb ovR/XeDktzFiU/fe9sUkQOqotuSJ+iefAvJ+BR0x4X4T39d64fi7Q0o5E9rjxQ0ehhov2CnR 5XbzZPKED8y/9Y1TeZlsLOQ3FScqsRRnJBpqMRcVJwIAd2zO8gwDAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: a.kesavan@samsung.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Leela Krishna Amudala Add generic cpu power control functions for exynos based SoCS for cpu power up/down and to know the cpu status. Signed-off-by: Leela Krishna Amudala Signed-off-by: Abhilash Kesavan --- arch/arm/mach-exynos/common.h | 3 +++ arch/arm/mach-exynos/pm.c | 36 ++++++++++++++++++++++++++++++++++++ arch/arm/mach-exynos/regs-pmu.h | 6 ++++++ 3 files changed, 45 insertions(+) diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 278b573..20adc2c 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -132,6 +132,9 @@ struct exynos_pmu_conf { }; extern void exynos_sys_powerdown_conf(enum sys_powerdown mode); +extern void exynos_cpu_power_down(int cpu); +extern void exynos_cpu_power_up(int cpu); +extern int exynos_cpu_power_state(int cpu); extern void s5p_init_cpu(void __iomem *cpuid_addr); extern unsigned int samsung_rev(void); diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index ca672e2..60c3356 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -99,6 +99,42 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) return -ENOENT; } +/** + * exynos_core_power_down : power down the specified cpu + * @cpu : the cpu to power down + * + * Power down the specified cpu. The sequence must be finished by a + * call to cpu_do_idle() + * + */ +void exynos_cpu_power_down(int cpu) +{ + __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); +} + +/** + * exynos_cpu_power_up : power up the specified cpu + * @cpu : the cpu to power up + * + * Power up the specified cpu + */ +void exynos_cpu_power_up(int cpu) +{ + __raw_writel(S5P_CORE_LOCAL_PWR_EN, + EXYNOS_ARM_CORE_CONFIGURATION(cpu)); +} + +/** + * exynos_cpu_power_state : returns the power state of the cpu + * @cpu : the cpu to retrieve the power state from + * + */ +int exynos_cpu_power_state(int cpu) +{ + return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) & + S5P_CORE_LOCAL_PWR_EN); +} + /* For Cortex-A9 Diagnostic and Power control register */ static unsigned int save_arm_register[2]; diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 4f6a256..84634ac 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -105,6 +105,12 @@ #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) #define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) +#define EXYNOS_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000) +#define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \ + (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr))) +#define EXYNOS_ARM_CORE_STATUS(_nr) \ + (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4) + #define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080) #define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084)