[v2,01/19] drm: sti: add bindings for DRM driver

Message ID 1400005588-3974-2-git-send-email-benjamin.gaignard@linaro.org
State New
Headers show

Commit Message

Benjamin Gaignard May 13, 2014, 6:26 p.m.
Add DRM/KMS driver bindings documentation.
Describe the required properties for each of the hardware IPs drivers.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
---
 .../devicetree/bindings/gpu/st,stih4xx.txt         | 187 +++++++++++++++++++++
 1 file changed, 187 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/gpu/st,stih4xx.txt

Patch hide | download patch | download mbox

diff --git a/Documentation/devicetree/bindings/gpu/st,stih4xx.txt b/Documentation/devicetree/bindings/gpu/st,stih4xx.txt
new file mode 100644
index 0000000..4755760
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/st,stih4xx.txt
@@ -0,0 +1,187 @@ 
+STMicroelectronics stih4xx platforms
+
+- sti-display-subsystem: Master device for DRM sub-components
+  This device must be the parent of all the sub-components and is responsible
+  of bind them.
+  Required properties:
+  - compatible: "st,sti-display-subsystem"
+  - ranges
+
+- sti-compositor: frame compositor engine
+  Required properties:
+  - compatible: "st,stih<chip>-compositor"
+  - reg: Physical base address of the IP registers and length of memory mapped region.
+  - clocks: from common clock binding: handle hardware IP needed clocks, the
+    number of clocks may depend of the SoC type.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names: names of the clocks listed in clocks property in the same
+    order.
+  - resets: resets to be used by the device
+    See ../reset/reset.txt for details.
+  - reset-names: names of the resets listed in resets property in the same
+    order.
+
+- sti-vtac: video timing advanced inter dye communication Rx and TX
+  Required properties:
+  - compatible: "st,stih<chip>-vtac-rx" or "st,stih<chip>-vtac-tx"
+  - reg: Physical base address of the IP registers and length of memory mapped region.
+  - reg-names: names of the mapped memory regions listed in regs property in
+    the same order.
+  - clocks: from common clock binding: handle hardware IP needed clocks, the
+    number of clocks may depend of the SoC type.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names: names of the clocks listed in clocks property in the same
+    order.
+  - vtac-rx-aux: Must be set to indicated that the device is dedicated to
+    auxillary data path if not the device is used for main data path.
+  - vtac-tx-aux: Must be set to indicated that the device is dedicated to
+    auxillary data path if not the device is used for main data path.
+
+- sti-vtg: video timing generator
+  Required properties:
+  - compatible: "st,stih<chip>-vtg"
+  - reg: Physical base address of the IP registers and length of memory mapped region.
+  - reg-names: names of the mapped memory regions listed in regs property in
+    the same order.
+  - interrupts : VTG interrupt number to the CPU.
+  - interrupt-names: name of the interrupts listed in interrupts property in
+    the same order.
+  - vtg-aux: Must be set to indicated that the device is dedicated to
+    auxillary data path if not the device is used for main data path.
+
+- sti-tvout: video out hardware block
+  Required properties:
+  - compatible: "st,stih<chip>-tvout"
+  - reg: Physical base address of the IP registers and length of memory mapped region.
+  - reg-names: names of the mapped memory regions listed in regs property in
+    the same order.
+  - resets: resets to be used by the device
+    See ../reset/reset.txt for details.
+  - reset-names: names of the resets listed in resets property in the same
+    order.
+  - ranges: to allow probing of subdevices
+
+- sti-hdmi: hdmi output block
+  Required properties:
+  - compatible: "st,stih<chip>-hdmi";
+  - reg: Physical base address of the IP registers and length of memory mapped region.
+  - reg-names: names of the mapped memory regions listed in regs property in
+    the same order.
+  - interrupts : HDMI interrupt number to the CPU.
+  - interrupt-names: name of the interrupts listed in interrupts property in
+    the same order
+  - clocks: from common clock binding: handle hardware IP needed clocks, the
+    number of clocks may depend of the SoC type.
+  - clock-names: names of the clocks listed in clocks property in the same
+    order.
+  - hdmi,hpd-gpio: gpio id to detect if an hdmi cable is plugged or not.
+
+sti-hda:
+  Required properties:
+  - compatible: "st,stih<chip>-hda"
+  - reg: Physical base address of the IP registers and length of memory mapped region.
+  - reg-names: names of the mapped memory regions listed in regs property in
+    the same order.
+  - clocks: from common clock binding: handle hardware IP needed clocks, the
+    number of clocks may depend of the SoC type.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names: names of the clocks listed in clocks property in the same
+    order.
+
+Example:
+
+/ {
+	...
+	sti-display-subsystem {
+		compatible = "st,sti-display-subsystem";
+		ranges;
+
+		sti-compositor@fd340000 {
+			compatible	= "st,stih416-compositor";
+			reg		= <0xfd340000 0x1000>;
+			clock-names	= "compo_main", "compo_aux",
+			                  "pix_main", "pix_aux";
+			clocks          = <&CLK_M_A2_DIV1 CLK_M_COMPO_MAIN>, <&CLK_M_A2_DIV1 CLK_M_COMPO_AUX>,
+					  <&CLOCKGEN_C_VCC CLK_S_PIX_MAIN>, <&CLOCKGEN_C_VCC CLK_S_PIX_AUX>;
+			reset-names     = "compo-main", "compo-aux";
+			resets          = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>;
+		};
+
+		sti-vtac-rx-main@fee82800 {
+			compatible	= "st,stih416-vtac-rx";
+			reg		= <0xfee82800 0x200>;
+			clock-names     = "vtac_main_phy";
+			clocks          = <&CLK_M_A2_DIV0 CLK_M_VTAC_MAIN_PHY>;
+		};
+
+		sti-vtac-rx-aux@fee82a00 {
+			compatible	= "st,stih416-vtac-rx";
+			reg		= <0xfee82a00 0x200>;
+			clock-names     = "vtac_aux_phy";
+			clocks          = <&CLK_M_A2_DIV0 CLK_M_VTAC_AUX_PHY>;
+			vtac-rx-aux;
+		};
+
+		sti-vtac-tx-main@fd349000 {
+			compatible	= "st,stih416-vtac-tx";
+			reg		= <0xfd349000 0x200>, <0xfd320000 0x10000>;
+			reg-names	= "vtac-tx", "vtac-phy";
+			clock-names     = "vtac_tx_phy";
+			clocks           = <&CLK_S_A1_HS CLK_S_VTAC_TX_PHY>;
+		};
+
+		sti-vtac-tx-aux@fd349200 {
+			compatible	= "st,stih416-vtac-tx";
+			reg		= <0xfd349200 0x200>, <0xfd320000 0x10000>;
+			reg-names	= "vtac-tx", "vtac-phy";
+			clock-names     = "vtac_tx_phy";
+			clocks          = <&CLK_S_A1_HS CLK_S_VTAC_TX_PHY>;
+			vtac-tx-aux;
+		};
+
+		sti-vtg-main@fd348000 {
+			compatible	= "st,stih416-vtg";
+			reg		= <0xfd348000 0x400>, <0xfe85A800 0x300>;
+			reg-names	= "master", "slave";
+			interrupts	= <GIC_SPI 175 IRQ_TYPE_NONE>;
+			interrupt-names = "synchro_irq";
+		};
+
+		sti-vtg-aux@fd348400 {
+			compatible	= "st,stih416-vtg";
+			reg		= <0xfd348400 0x400>, <0xfe858200 0x300>;
+			reg-names	= "master", "slave";
+			interrupts	= <GIC_SPI 176 IRQ_TYPE_NONE>;
+			interrupt-names = "synchro_irq";
+			vtg-aux;
+		};
+
+		sti-tvout@fe000000 {
+			compatible	= "st,stih416-tvout";
+			reg		= <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>;
+			reg-names	= "tvout-reg", "hda-reg", "syscfg";
+			reset-names     = "tvout";
+			resets          = <&softreset STIH416_HDTVOUT_SOFTRESET>;
+		};
+
+		sti-hdmi@fe85c000 {
+			compatible	= "st,stih416-hdmi";
+			reg		= <0xfe85c000 0x1000>, <0xfe830000 0x10000>;
+			reg-names	= "hdmi-reg", "syscfg";
+			interrupts	= <GIC_SPI 173 IRQ_TYPE_NONE>;
+			interrupt-names	= "hdmi_irq";
+		        clock-names	= "hdmi_pix", "hdmi_tmds", "hdmi_phy", "hdmi_audio";
+			clocks          = <&CLOCKGEN_C_VCC CLK_S_PIX_HDMI>, <&CLOCKGEN_C_VCC CLK_S_TMDS_HDMI>, <&CLOCKGEN_C_VCC CLK_S_HDMI_REJECT_PLL>, <&CLOCKGEN_B1 CLK_S_PCM_0>;
+			hdmi,hpd-gpio	= <&PIO2 5>;
+		};
+
+		sti-hda@fe85a000 {
+			compatible	= "st,stih416-hda";
+			reg		= <0xfe85a000 0x400>, <0xfe83085c 0x4>;
+			reg-names	= "hda-reg", "video-dacs-ctrl";
+			clock-names	= "hda_pix", "hda_hddac";
+			clocks          = <&CLOCKGEN_C_VCC CLK_S_PIX_HD>, <&CLOCKGEN_C_VCC CLK_S_HDDAC>;
+		};
+	};
+	...
+};