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[209.132.180.67]) by mx.google.com with ESMTP id gv5si1116930pac.217.2014.05.14.01.04.36; Wed, 14 May 2014 01:04:36 -0700 (PDT) Received-SPF: none (google.com: linux-samsung-soc-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753203AbaENIEa (ORCPT + 9 others); Wed, 14 May 2014 04:04:30 -0400 Received: from mail-pa0-f43.google.com ([209.85.220.43]:57224 "EHLO mail-pa0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752356AbaENIEY (ORCPT ); Wed, 14 May 2014 04:04:24 -0400 Received: by mail-pa0-f43.google.com with SMTP id hz1so1379586pad.2 for ; Wed, 14 May 2014 01:04:23 -0700 (PDT) X-Received: by 10.66.164.70 with SMTP id yo6mr2444476pab.85.1400054663615; Wed, 14 May 2014 01:04:23 -0700 (PDT) Received: from localhost.localdomain ([14.140.216.146]) by mx.google.com with ESMTPSA id as12sm4807422pac.43.2014.05.14.01.04.19 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 14 May 2014 01:04:23 -0700 (PDT) From: Chander Kashyap To: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: daniel.lezcano@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, kgene.kim@samsung.com, Chander Kashyap , Chander Kashyap Subject: [PATCH v5 2/6] arm: exynos: add generic function to calculate cpu number Date: Wed, 14 May 2014 13:33:53 +0530 Message-Id: <1400054637-21505-3-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1400054637-21505-1-git-send-email-chander.kashyap@linaro.org> References: <1400054637-21505-1-git-send-email-chander.kashyap@linaro.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: chander.kashyap@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.174 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The address of cpu power registers in pmu is based on cpu number offsets. This function calculate the same. This is essentially required in case of multi-cluster SoC's e.g Exynos5420. Signed-off-by: Chander Kashyap Signed-off-by: Chander Kashyap --- arch/arm/mach-exynos/regs-pmu.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 4179f6a..485aefd 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -325,4 +325,13 @@ #define EXYNOS5420_SWRESET_KFC_SEL 0x3 +#include +#define MAX_CPUS_IN_CLUSTER 4 + +static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr) +{ + return ((MPIDR_AFFINITY_LEVEL(mpidr, 1) * MAX_CPUS_IN_CLUSTER) + + MPIDR_AFFINITY_LEVEL(mpidr, 0)); +} + #endif /* __ASM_ARCH_REGS_PMU_H */