diff mbox series

[RFC,v2,2/4] target/mips: Store number of TLB entries in CPUMIPSState

Message ID 20201015224746.540027-3-f4bug@amsat.org
State New
Headers show
Series target/mips: Make the number of TLB entries a CPU property | expand

Commit Message

Philippe Mathieu-Daudé Oct. 15, 2020, 10:47 p.m. UTC 
As we want to make the number of TLB entries configurable,
store it in CPUMIPSState. Introduce the init_tlb_entries()
helper which initializes it from the CP0C1_MMU config content.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/cpu.h                |  1 +
 target/mips/translate.c          | 13 ++++++++++++-
 target/mips/translate_init.c.inc |  2 +-
 3 files changed, 14 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 7cf7f5239f7..b84e9a8fcae 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1140,6 +1140,7 @@  struct CPUMIPSState {
 #endif
 
     const mips_def_t *cpu_model;
+    uint8_t tlb_entries;
     void *irq[8];
     QEMUTimer *timer; /* Internal timer */
     struct MIPSITUState *itu;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4c9b6216321..698bcee8915 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31316,8 +31316,18 @@  void mips_tcg_init(void)
 
 #include "translate_init.c.inc"
 
+static bool init_tlb_entries(CPUMIPSState *env, Error **errp)
+{
+    env->tlb_entries = 1 + extract32(env->cpu_model->CP0_Config1, CP0C1_MMU, 6);
+
+    return true;
+}
+
 bool cpu_mips_realize_env(CPUMIPSState *env, Error **errp)
 {
+    if (!init_tlb_entries(env, errp)) {
+        return false;
+    }
     env->exception_base = (int32_t)0xBFC00000;
 
 #ifndef CONFIG_USER_ONLY
@@ -31357,7 +31367,8 @@  void cpu_state_reset(CPUMIPSState *env)
 #ifdef TARGET_WORDS_BIGENDIAN
     env->CP0_Config0 |= (1 << CP0C0_BE);
 #endif
-    env->CP0_Config1 = env->cpu_model->CP0_Config1;
+    env->CP0_Config1 = deposit32(env->cpu_model->CP0_Config1, CP0C1_MMU, 6,
+                                 env->tlb_entries - 1);
     env->CP0_Config2 = env->cpu_model->CP0_Config2;
     env->CP0_Config3 = env->cpu_model->CP0_Config3;
     env->CP0_Config4 = env->cpu_model->CP0_Config4;
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index 637caccd890..a426463c434 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -946,7 +946,7 @@  static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 
 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 {
-    env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
+    env->tlb->nb_tlb = env->tlb_entries;
     env->tlb->map_address = &r4k_map_address;
     env->tlb->helper_tlbwi = r4k_helper_tlbwi;
     env->tlb->helper_tlbwr = r4k_helper_tlbwr;