| Message ID | 20201013132535.3599453-4-f4bug@amsat.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/mips: Make the number of TLB entries a CPU property | expand |
在 2020/10/13 21:25, Philippe Mathieu-Daudé 写道: > Allow changing the number of TLB entries for > testing/tunning purpose. > > Example to force a 34Kf cpu with 64 TLB: > > $ qemu-system-mipsel -cpu 34Kf,tlb-entries=64 ... > > This is helpful for developers of the Yocto Project [*]: > > Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit > MIPS CI loop. It was observed that in this case CI test execution > time was almost twice longer than 64bit MIPS variant that runs > under MIPS64R2-generic model. It was investigated and concluded > that the difference in number of TLBs 16 in 34Kf case vs 64 in > MIPS64R2-generic is responsible for most of CI real time execution > difference. Because with 16 TLBs linux user-land trashes TLB more > and it needs to execute more instructions in TLB refill handler > calls, as result it runs much longer. > > [*] https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html > > Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992 > Reported-by: Victor Kamensky <kamensky@cisco.com> > Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- Hi Philippe, I think name can this property vtlb-entries? MIPS R2 had introduced dual-TLB feature and the entries specified here is the number of VTLB, while FTLB is another set of entries with fixed pagesize. Although MIPS TCG haven't implemented dual-TLB but it can prevent future confusion. Thanks. - Jiaxun
diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 117c748345e..da31831368b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -26,7 +26,7 @@ #include "qemu/module.h" #include "sysemu/kvm.h" #include "exec/exec-all.h" - +#include "hw/qdev-properties.h" static void mips_cpu_set_pc(CPUState *cs, vaddr value) { @@ -183,6 +183,11 @@ static ObjectClass *mips_cpu_class_by_name(const char *cpu_model) return oc; } +static Property mips_cpu_properties[] = { + DEFINE_PROP_UINT8("tlb-entries", MIPSCPU, env.tlb_entries, 0), + DEFINE_PROP_END_OF_LIST() +}; + static void mips_cpu_class_init(ObjectClass *c, void *data) { MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); @@ -192,6 +197,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset); + device_class_set_props(dc, mips_cpu_properties); cc->class_by_name = mips_cpu_class_by_name; cc->has_work = mips_cpu_has_work; diff --git a/target/mips/translate.c b/target/mips/translate.c index 9d13e164c2e..70e45b0f7ec 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -39,6 +39,7 @@ #include "exec/translator.h" #include "exec/log.h" #include "qemu/qemu-print.h" +#include "qapi/error.h" #define MIPS_DEBUG_DISAS 0 @@ -31319,7 +31320,14 @@ void mips_tcg_init(void) bool cpu_mips_realize_env(CPUMIPSState *env, Error **errp) { env->exception_base = (int32_t)0xBFC00000; - env->tlb_entries = 1 + extract32(env->cpu_model->CP0_Config1, CP0C1_MMU, 6); + if (!env->tlb_entries) { + env->tlb_entries = 1 + extract32(env->cpu_model->CP0_Config1, + CP0C1_MMU, 6); + } else if (env->tlb_entries > 64) { + error_setg(errp, "Invalid value '%d' for property 'tlb-entries'", + env->tlb_entries); + return false; + } #ifndef CONFIG_USER_ONLY mmu_init(env, env->cpu_model);
Allow changing the number of TLB entries for testing/tunning purpose. Example to force a 34Kf cpu with 64 TLB: $ qemu-system-mipsel -cpu 34Kf,tlb-entries=64 ... This is helpful for developers of the Yocto Project [*]: Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit MIPS CI loop. It was observed that in this case CI test execution time was almost twice longer than 64bit MIPS variant that runs under MIPS64R2-generic model. It was investigated and concluded that the difference in number of TLBs 16 in 34Kf case vs 64 in MIPS64R2-generic is responsible for most of CI real time execution difference. Because with 16 TLBs linux user-land trashes TLB more and it needs to execute more instructions in TLB refill handler calls, as result it runs much longer. [*] https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992 Reported-by: Victor Kamensky <kamensky@cisco.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- target/mips/cpu.c | 8 +++++++- target/mips/translate.c | 10 +++++++++- 2 files changed, 16 insertions(+), 2 deletions(-)