From patchwork Fri Mar 4 10:13:15 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jason Liu X-Patchwork-Id: 309 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:41:38 -0000 Delivered-To: patches@linaro.org Received: by 10.224.60.68 with SMTP id o4cs9464qah; Fri, 4 Mar 2011 02:13:16 -0800 (PST) Received: by 10.43.65.1 with SMTP id xk1mr355592icb.294.1299233595513; Fri, 04 Mar 2011 02:13:15 -0800 (PST) Received: from mail-iw0-f178.google.com (mail-iw0-f178.google.com [209.85.214.178]) by mx.google.com with ESMTPS id hj39si4923657ibb.76.2011.03.04.02.13.15 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 04 Mar 2011 02:13:15 -0800 (PST) Received-SPF: pass (google.com: domain of liu.h.jason@gmail.com designates 209.85.214.178 as permitted sender) client-ip=209.85.214.178; Authentication-Results: mx.google.com; spf=pass (google.com: domain of liu.h.jason@gmail.com designates 209.85.214.178 as permitted sender) smtp.mail=liu.h.jason@gmail.com; dkim=pass (test mode) header.i=@gmail.com Received: by mail-iw0-f178.google.com with SMTP id 9so2237867iwn.37 for ; Fri, 04 Mar 2011 02:13:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:in-reply-to:references:date :message-id:subject:from:to:content-type:content-transfer-encoding; bh=S8sM9yAR+67QCB/lgCo0+zSYQ++or/9dQ6m1d9iluX4=; b=Xe1Qg2nWAaN4uYcdBud+pc/D9w4qKGUkjn+oa5c+8Y1eQdP5ryg421DQpMcJV7sixH c4th9189wViWWxkxyLi0Ml4IbIFqtofWQywcUc+VDcn7ssdrUHjvsgsSM/l4MQVr2Ck/ aXgzxWHiRsM0dZZb23IUPT0HZ2k6KyV/jDBRg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :content-type:content-transfer-encoding; b=oiEnFvLgLHXCBr5dJ2dEMno0TT2wsUR802UOcwnAHiBXBP73Wj1dh6anvdE1Om7pOR DjbQ0y5HY3PiTODmvfKT5CXARtSj1kLK2cYwiGue7rpXgCh0JDcef6fOCEAsMoBAQS2D waG5IVvc6bOlUXMwROAXdC0KJfGI3GHuRMUfY= MIME-Version: 1.0 Received: by 10.42.164.195 with SMTP id h3mr253788icy.464.1299233595149; Fri, 04 Mar 2011 02:13:15 -0800 (PST) Received: by 10.42.227.4 with HTTP; Fri, 4 Mar 2011 02:13:15 -0800 (PST) In-Reply-To: <1298445970-9670-2-git-send-email-r64343@freescale.com> References: <1298445970-9670-1-git-send-email-r64343@freescale.com> <1298445970-9670-2-git-send-email-r64343@freescale.com> Date: Fri, 4 Mar 2011 18:13:15 +0800 Message-ID: Subject: Fwd: [U-Boot] [PATCH V2 1/1] MX53: support for freescale MX53LOCO board From: Jason Liu To: patches@linaro.org ---------- Forwarded message ---------- From: Jason Liu Date: 2011/2/23 Subject: [U-Boot] [PATCH V2 1/1] MX53: support for freescale MX53LOCO board To: u-boot@lists.denx.de This patch add initial support for freescale MX53LOCO board. Network(FEC),SD/MMC, UART have been supported by this patch. Signed-off-by: Jason Liu --- Changes for v2: - remove config.mk, instead add CONFIG_ options in boards.cfg - fix copyright issue, use freescale copyright. - rebase on u-boot-imx/next branch and resend. ---  MAINTAINERS                           |    1 +  board/freescale/mx53loco/Makefile     |   47 +++++  board/freescale/mx53loco/imximage.cfg |   96 ++++++++++  board/freescale/mx53loco/mx53loco.c   |  316 +++++++++++++++++++++++++++++++++  boards.cfg                            |    1 +  include/configs/mx53loco.h            |  196 ++++++++++++++++++++  6 files changed, 657 insertions(+), 0 deletions(-) -- 1.7.0.4 diff --git a/MAINTAINERS b/MAINTAINERS index b37ed0c..0462179 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -566,6 +566,7 @@ Stefano Babic  Jason Liu        mx53evk         i.MX53 +       mx53loco        i.MX53  Enric Balletbo i Serra diff --git a/board/freescale/mx53loco/Makefile b/board/freescale/mx53loco/Makefile new file mode 100644 index 0000000..2088a48 --- /dev/null +++ b/board/freescale/mx53loco/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# Jason Liu +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB    = $(obj)lib$(BOARD).o + +COBJS  := mx53loco.o + +SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS   := $(addprefix $(obj),$(COBJS)) +SOBJS  := $(addprefix $(obj),$(SOBJS)) + +$(LIB):        $(obj).depend $(OBJS) $(SOBJS) +       $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: +       rm -f $(SOBJS) $(OBJS) + +distclean:     clean +       rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx53loco/imximage.cfg b/board/freescale/mx53loco/imximage.cfg new file mode 100755 index 0000000..ce9c8fc --- /dev/null +++ b/board/freescale/mx53loco/imximage.cfg @@ -0,0 +1,96 @@ +# Copyright (C) 2011 Freescale Semiconductor, Inc. +# Jason Liu +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer docs/README.imxmage for more details about how-to configure +# and create imximage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# image version + +IMAGE_VERSION 2 + +# Boot Device : one of +# spi, sd (the board has no nand neither onenand) + +BOOT_FROM      sd + +# Device Configuration Data (DCD) +# +# Each entry must have the format: +# Addr-type           Address        Value +# +# where: +#      Addr-type register length (1,2 or 4 bytes) +#      Address   absolute address of the register +#      value     value to be stored in the register + +DATA 4 0x53fa8554 0x00300000 +DATA 4 0x53fa8558 0x00300040 +DATA 4 0x53fa8560 0x00300000 +DATA 4 0x53fa8564 0x00300040 +DATA 4 0x53fa8568 0x00300040 +DATA 4 0x53fa8570 0x00300000 +DATA 4 0x53fa8574 0x00300000 +DATA 4 0x53fa8578 0x00300000 +DATA 4 0x53fa857c 0x00300040 +DATA 4 0x53fa8580 0x00300040 +DATA 4 0x53fa8584 0x00300000 +DATA 4 0x53fa8588 0x00300000 +DATA 4 0x53fa8590 0x00300040 +DATA 4 0x53fa8594 0x00300000 +DATA 4 0x53fa86f0 0x00300000 +DATA 4 0x53fa86f4 0x00000000 +DATA 4 0x53fa86fc 0x00000000 +DATA 4 0x53fa8714 0x00000000 +DATA 4 0x53fa8718 0x00300000 +DATA 4 0x53fa871c 0x00300000 +DATA 4 0x53fa8720 0x00300000 +DATA 4 0x53fa8724 0x04000000 +DATA 4 0x53fa8728 0x00300000 +DATA 4 0x53fa872c 0x00300000 +DATA 4 0x63fd9088 0x35343535 +DATA 4 0x63fd9090 0x4d444c44 +DATA 4 0x63fd907c 0x01370138 +DATA 4 0x63fd9080 0x013b013c +DATA 4 0x63fd9018 0x00011740 +DATA 4 0x63fd9000 0xc3190000 +DATA 4 0x63fd900c 0x9f5152e3 +DATA 4 0x63fd9010 0xb68e8a63 +DATA 4 0x63fd9014 0x01ff00db +DATA 4 0x63fd902c 0x000026d2 +DATA 4 0x63fd9030 0x009f0e21 +DATA 4 0x63fd9008 0x12273030 +DATA 4 0x63fd9004 0x0002002d +DATA 4 0x63fd901c 0x00008032 +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00028031 +DATA 4 0x63fd901c 0x092080b0 +DATA 4 0x63fd901c 0x04008040 +DATA 4 0x63fd901c 0x0000803a +DATA 4 0x63fd901c 0x0000803b +DATA 4 0x63fd901c 0x00028039 +DATA 4 0x63fd901c 0x09208138 +DATA 4 0x63fd901c 0x04008048 +DATA 4 0x63fd9020 0x00001800 +DATA 4 0x63fd9040 0x04b80003 +DATA 4 0x63fd9058 0x00022227 +DATA 4 0x63fd901c 0x00000000 diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c new file mode 100755 index 0000000..fd56c3d --- /dev/null +++ b/board/freescale/mx53loco/mx53loco.c @@ -0,0 +1,316 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +u32 get_board_rev(void) +{ +       return get_cpu_rev(); +} + +int dram_init(void) +{ +       gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, +                               PHYS_SDRAM_1_SIZE); + +       return 0; +} +void dram_init_banksize(void) +{ +       gd->bd->bi_dram[0].start = PHYS_SDRAM_1; +       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + +       gd->bd->bi_dram[1].start = PHYS_SDRAM_2; +       gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +} + +static void setup_iomux_uart(void) +{ +       /* UART1 RXD */ +       mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2); +       mxc_iomux_set_pad(MX53_PIN_CSI0_D11, +                               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | +                               PAD_CTL_ODE_OPENDRAIN_ENABLE); +       mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1); + +       /* UART1 TXD */ +       mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2); +       mxc_iomux_set_pad(MX53_PIN_CSI0_D10, +                               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU | +                               PAD_CTL_ODE_OPENDRAIN_ENABLE); +} + +static void setup_iomux_fec(void) +{ +       /*FEC_MDIO*/ +       mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0); +       mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, +                               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); +       mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1); + +       /*FEC_MDC*/ +       mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0); +       mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH); + +       /* FEC RXD1 */ +       mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0); +       mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, +                       PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + +       /* FEC RXD0 */ +       mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0); +       mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, +                       PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + +        /* FEC TXD1 */ +       mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0); +       mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH); + +       /* FEC TXD0 */ +       mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0); +       mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH); + +       /* FEC TX_EN */ +       mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0); +       mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH); + +       /* FEC TX_CLK */ +       mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0); +       mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, +                       PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + +       /* FEC RX_ER */ +       mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0); +       mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, +                       PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + +       /* FEC CRS */ +       mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0); +       mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, +                       PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[2] = { +       {MMC_SDHC1_BASE_ADDR, 1}, +       {MMC_SDHC3_BASE_ADDR, 1}, +}; + +int board_mmc_getcd(u8 *cd, struct mmc *mmc) +{ +       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + +       if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) +               *cd = mxc_gpio_get(77); /*GPIO3_13*/ +       else +               *cd = mxc_gpio_get(75); /*GPIO3_11*/ + +       return 0; +} + +int board_mmc_init(bd_t *bis) +{ +       u32 index; +       s32 status = 0; + +       for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { +               switch (index) { +               case 0: +                       mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); +                       mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); +                       mxc_request_iomux(MX53_PIN_SD1_DATA0, +                                               IOMUX_CONFIG_ALT0); +                       mxc_request_iomux(MX53_PIN_SD1_DATA1, +                                               IOMUX_CONFIG_ALT0); +                       mxc_request_iomux(MX53_PIN_SD1_DATA2, +                                               IOMUX_CONFIG_ALT0); +                       mxc_request_iomux(MX53_PIN_SD1_DATA3, +                                               IOMUX_CONFIG_ALT0); +                       mxc_request_iomux(MX53_PIN_EIM_DA13, +                                               IOMUX_CONFIG_ALT1); + +                       mxc_iomux_set_pad(MX53_PIN_SD1_CMD, +                               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); +                       mxc_iomux_set_pad(MX53_PIN_SD1_CLK, +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | +                               PAD_CTL_DRV_HIGH); +                       mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, +                               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); +                       mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, +                               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); +                       mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, +                               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); +                       mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, +                               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); +                       break; +               case 1: +                       mxc_request_iomux(MX53_PIN_ATA_RESET_B, +                                               IOMUX_CONFIG_ALT2); +                       mxc_request_iomux(MX53_PIN_ATA_IORDY, +                                               IOMUX_CONFIG_ALT2); +                       mxc_request_iomux(MX53_PIN_ATA_DATA8, +                                               IOMUX_CONFIG_ALT4); +                       mxc_request_iomux(MX53_PIN_ATA_DATA9, +                                               IOMUX_CONFIG_ALT4); +                       mxc_request_iomux(MX53_PIN_ATA_DATA10, +                                               IOMUX_CONFIG_ALT4); +                       mxc_request_iomux(MX53_PIN_ATA_DATA11, +                                               IOMUX_CONFIG_ALT4); +                       mxc_request_iomux(MX53_PIN_ATA_DATA0, +                                               IOMUX_CONFIG_ALT4); +                       mxc_request_iomux(MX53_PIN_ATA_DATA1, +                                               IOMUX_CONFIG_ALT4); +                       mxc_request_iomux(MX53_PIN_ATA_DATA2, +                                               IOMUX_CONFIG_ALT4); +                       mxc_request_iomux(MX53_PIN_ATA_DATA3, +                                               IOMUX_CONFIG_ALT4); +                       mxc_request_iomux(MX53_PIN_EIM_DA11, +                                               IOMUX_CONFIG_ALT1); + +                       mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, +                               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); +                       mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | +                               PAD_CTL_DRV_HIGH); +                       mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, +                               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); +                       mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, +                               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); +                       mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, +                               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); +                       mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, +                               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); +                       mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, +                               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); +                       mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, +                               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); +                       mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, +                               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); +                       mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, +                               PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | +                               PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | +                               PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + +                       break; +               default: +                       printf("Warning: you configured more ESDHC controller" +                               "(%d) as supported by the board(2)\n", +                               CONFIG_SYS_FSL_ESDHC_NUM); +                       return status; +               } +               status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]); +       } + +       return status; +} +#endif + +int board_early_init_f(void) +{ +       setup_iomux_uart(); +       setup_iomux_fec(); + +       return 0; +} + +int board_init(void) +{ +       gd->bd->bi_arch_number = MACH_TYPE_MX53_LOCO; +       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + +       return 0; +} + +int checkboard(void) +{ +       u32 cause; +       struct src *src_regs = (struct src *)SRC_BASE_ADDR; + +       puts("Board: MX53LOCO ["); + +       cause = src_regs->srsr; +       switch (cause) { +       case 0x0001: +               printf("POR"); +               break; +       case 0x0009: +               printf("RST"); +               break; +       case 0x0010: +       case 0x0011: +               printf("WDOG"); +               break; +       default: +               printf("unknown"); +       } +       printf("]\n"); +       return 0; +} diff --git a/boards.cfg b/boards.cfg index b85ad35..6f926b0 100644 --- a/boards.cfg +++ b/boards.cfg @@ -109,6 +109,7 @@ ca9x4_ct_vxp                 arm         armv7   vexpress            armltd  efikamx                      arm         armv7       efikamx   -              mx5  mx51evk                      arm         armv7       mx51evk   freescale      mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg  mx53evk                      arm         armv7       mx53evk   freescale      mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg +mx53loco                     arm         armv7       mx53loco    freescale      mx5 mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg  vision2                      arm         armv7       vision2   ttcontrol      mx5  cm_t35                       arm         armv7       cm_t35    -              omap3  omap3_overo                  arm         armv7       overo   -              omap3 diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h new file mode 100644 index 0000000..8c30012 --- /dev/null +++ b/include/configs/mx53loco.h @@ -0,0 +1,196 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu + * + * Configuration settings for Freescale MX53 low cost board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MX53 + +#define CONFIG_SYS_MX5_HCLK    24000000 +#define CONFIG_SYS_MX5_CLK32           32768 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_L2_OFF + +#include + +#define CONFIG_CMDLINE_TAG             1       /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG            1 +#define CONFIG_SETUP_MEMORY_TAGS       1 +#define CONFIG_INITRD_TAG              1 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 2 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX53_UART1 + +/* I2C Configs */ +#define CONFIG_CMD_I2C          1 +#define CONFIG_HARD_I2C         1 +#define CONFIG_I2C_MXC          1 +#define CONFIG_SYS_I2C_MX53_PORT2       1 +#define CONFIG_SYS_I2C_SPEED            100000 +#define CONFIG_SYS_I2C_SLAVE            0xfe + +/* PMIC Configs */ +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_I2C +#define CONFIG_SYS_FSL_PMIC_I2C_ADDR    8 + +/* MMC Configs */ +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR      0 +#define CONFIG_SYS_FSL_ESDHC_NUM       2 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +/* Eth Configs */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE   FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1F + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX              1 +#define CONFIG_BAUDRATE                        115200 +#define CONFIG_SYS_BAUDRATE_TABLE      {9600, 19200, 38400, 57600, 115200} + +/* Command definition */ +#include + +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY       3 + +#define CONFIG_PRIME   "FEC0" + +#define CONFIG_LOADADDR                0x70800000      /* loadaddr env var */ +#define CONFIG_SYS_TEXT_BASE    0x77800000 + +#define CONFIG_EXTRA_ENV_SETTINGS \ +       "script=boot.scr\0" \ +       "uimage=uImage\0" \ +       "mmcdev=0\0" \ +       "mmcpart=2\0" \ +       "mmcroot=/dev/mmcblk0p3 rw\0" \ +       "mmcrootfstype=ext3 rootwait\0" \ +       "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ +               "root=${mmcroot} " \ +               "rootfstype=${mmcrootfstype}\0" \ +       "loadbootscript=" \ +               "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ +       "bootscript=echo Running bootscript from mmc ...; " \ +               "source\0" \ +       "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ +       "mmcboot=echo Booting from mmc ...; " \ +               "run mmcargs; " \ +               "bootm\0" \ +       "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ +               "root=/dev/nfs " \ +               "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ +       "netboot=echo Booting from net ...; " \ +               "run netargs; " \ +               "dhcp ${uimage}; bootm\0" \ + +#define CONFIG_BOOTCOMMAND \ +       "if mmc rescan ${mmcdev}; then " \ +               "if run loadbootscript; then " \ +                       "run bootscript; " \ +               "else " \ +                       "if run loaduimage; then " \ +                               "run mmcboot; " \ +                       "else run netboot; " \ +                       "fi; " \ +               "fi; " \ +       "else run netboot; fi" + +#define CONFIG_ARP_TIMEOUT     200UL + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP            /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER         /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2     "> " +#define CONFIG_SYS_PROMPT              "MX53LOCO U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE              256     /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS     16      /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START       0x70000000 +#define CONFIG_SYS_MEMTEST_END         0x10000 + +#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR + +#define CONFIG_SYS_HZ          1000 +#define CONFIG_CMDLINE_EDITING + +/* Stack sizes */ +#define CONFIG_STACKSIZE       (128 * 1024)    /* regular stack */ + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS   2 +#define PHYS_SDRAM_1           CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE      (512 * 1024 * 1024) +#define PHYS_SDRAM_2           CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE      (512 * 1024 * 1024) +#define PHYS_SDRAM_SIZE         (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) + +#define CONFIG_SYS_SDRAM_BASE          (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR       (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE       (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ +       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ +       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_OFFSET      (6 * 64 * 1024) +#define CONFIG_ENV_SIZE        (8 * 1024) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 + +#endif                         /* __CONFIG_H */