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[4/4] ARM 64 bit sync atomic operations [V2]

Message ID 20110726090228.GE6925@davesworkthinkpad
State Superseded
Headers show

Commit Message

Dr. David Alan Gilbert July 26, 2011, 9:02 a.m. UTC 
gcc/
    	* config/arm/arm.c (TARGET_HAVE_DMB_MCR) MCR Not available in Thumb1
    	  but is available on armv6

Comments

Ramana Radhakrishnan Aug. 1, 2011, 3:43 p.m. UTC | #1 
On 26 July 2011 10:02, Dr. David Alan Gilbert <david.gilbert@linaro.org> wrote:
>
>        gcc/
>        * config/arm/arm.c (TARGET_HAVE_DMB_MCR) MCR Not available in Thumb1
>          but is available on armv6

`:' after (TARGET_HAVE_DMB_MCR) and something like

`Disable for Thumb1.'

instead of what's on there.

>
>  /* Nonzero if this chip implements a memory barrier via CP15.  */
> -#define TARGET_HAVE_DMB_MCR    (arm_arch6k && ! TARGET_HAVE_DMB)
> +#define TARGET_HAVE_DMB_MCR    (arm_arch6 && ! TARGET_HAVE_DMB \
> +                                && ! TARGET_THUMB1)

Otherwise OK for trunk and afflicted release branches since this
really is a bug fix.

cheers
Ramana
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Patch

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 0d419d5..146b9ad 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -285,7 +285,8 @@  extern void (*arm_lang_output_object_attributes_hook)(void);
 #define TARGET_HAVE_DMB		(arm_arch7)
 
 /* Nonzero if this chip implements a memory barrier via CP15.  */
-#define TARGET_HAVE_DMB_MCR	(arm_arch6k && ! TARGET_HAVE_DMB)
+#define TARGET_HAVE_DMB_MCR	(arm_arch6 && ! TARGET_HAVE_DMB \
+				 && ! TARGET_THUMB1)
 
 /* Nonzero if this chip implements a memory barrier instruction.  */
 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)