[v4,1/2] ARMV7: Add support for Samsung ORIGEN board

Message ID 1311914519-10531-2-git-send-email-chander.kashyap@linaro.org
State Superseded
Headers show

Commit Message

Chander Kashyap July 29, 2011, 4:41 a.m.
Origen board is based upon S5PV310 SoC which is similiar to
S5PC210 SoC.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
---
Changes for v2:
	- None
Changes for v3:
	- Board entry added Alphabetically in boards.cfg
	- Used get_Ram_size function to calculate ram size
Changes for v4:
	- CONFIG_MACH_TYPE defined to initialise MACH_TYPE in generic way
	- Used s5p_gpio_* functions for gpio operations

 MAINTAINERS                          |    1 +
 board/samsung/origen/Makefile        |   46 ++++
 board/samsung/origen/lowlevel_init.S |  464 ++++++++++++++++++++++++++++++++++
 board/samsung/origen/mem_setup.S     |  359 ++++++++++++++++++++++++++
 board/samsung/origen/origen.c        |  105 ++++++++
 boards.cfg                           |    1 +
 include/configs/origen.h             |  166 ++++++++++++
 7 files changed, 1142 insertions(+), 0 deletions(-)
 create mode 100644 board/samsung/origen/Makefile
 create mode 100644 board/samsung/origen/lowlevel_init.S
 create mode 100644 board/samsung/origen/mem_setup.S
 create mode 100644 board/samsung/origen/origen.c
 create mode 100644 include/configs/origen.h

Comments

Wolfgang Denk July 31, 2011, 10 a.m. | #1
Dear Chander Kashyap,

In message <1311914519-10531-2-git-send-email-chander.kashyap@linaro.org> you wrote:
> Origen board is based upon S5PV310 SoC which is similiar to
> S5PC210 SoC.
> 
> Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
...
> +	/* APLL(1), MPLL(1), CORE(0), HPM(0) */
> +	ldr	r1, =0x0101
> +	ldr	r2, =0x14200			@CLK_SRC_CPU
...
> +	mov	r1, #0x10000
...
> +	ldr	r1, =0x00
> +	ldr	r2, =0x0C210			@CLK_SRC_TOP0
...
> +	ldr	r1, =0x00
> +	ldr	r2, =0x0C214			@CLK_SRC_TOP1_OFFSET
...
> +	ldr	r1, =0x10000
> +	ldr	r2, =0x10200			@CLK_SRC_DMC_OFFSET
...

..
> +	/*
> +	 * CLK_DIV_DMC0:
> +	 *
> +	 * CORE_TIMERS_RATIO[28]	0x1
> +	 * COPY2_RATIO[24]		0x3
> +	 * DMCP_RATIO[20]		0x1
> +	 * DMCD_RATIO[16]		0x1
> +	 * DMC_RATIO[12]		0x1
> +	 * DPHY_RATIO[8]		0x1
> +	 * ACP_PCLK_RATIO[4]		0x1
> +	 * ACP_RATIO[0]			0x3
> +	 */
> +	ldr	r1, =0x13111113
> +	ldr	r2, =0x010500			@CLK_DIV_DMC0_OFFSET
> +	str	r1, [r0, r2]


lease get rid of all these magic hard coded constants.  Use symbolic
names instead. If needed, auto-generate these from the respective C
structs.  If needed, create the C structs.

...
> --- /dev/null
> +++ b/board/samsung/origen/mem_setup.S
> @@ -0,0 +1,359 @@

What exactly is the reeason for not coding this in C ?

...
> +#ifdef CONFIG_MIU_1BIT_12_INTERLEAVED
> +	ldr	r1, =0x0000000c
> +	str	r1, [r0, #0x400]
> +	ldr	r1, =0x00000001
> +	str	r1, [r0, #0xc00]
> +#elif defined(CONFIG_MIU_1BIT_7_INTERLEAVED)
> +	ldr	r1, =0x00000007
> +	str	r1, [r0, #0x400]
> +	ldr	r1, =0x00000001
> +	str	r1, [r0, #0xc00]
> +#elif defined(CONFIG_MIU_2BIT_21_12_INTERLEAVED)
> +	ldr	r1, =0x2000150c
> +	str	r1, [r0, #0x400]
> +	ldr	r1, =0x00000001
> +	str	r1, [r0, #0xc00]
> +#elif defined(CONFIG_MIU_2BIT_21_7_INTERLEAVED)
> +	ldr	r1, =0x20001507
> +	str	r1, [r0, #0x400]
> +	ldr	r1, =0x00000001
> +	str	r1, [r0, #0xc00]
> +#elif defined(CONFIG_MIU_2BIT_31_INTERLEAVED)
> +	ldr	r1, =0x0000001d
> +	str	r1, [r0, #0x400]
> +	ldr	r1, =0x00000001
> +	str	r1, [r0, #0xc00]

See above.  Please get rid of all these hard-ciooded magic numbers.
[Eventually this happens automativcally when you rewrite this in C.]

> +int dram_init(void)
> +{
> +	gd->ram_size	= get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
> +			+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
> +			+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
> +			+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
> +
> +	return 0;
> +}
> +
> +void dram_init_banksize(void)
> +{
> +	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> +	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> +	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
> +	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
> +	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
> +	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
> +	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
> +	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
> +}

How do you detect memory issues in one of the memory banks, say, a
memory error in bank 3?

> diff --git a/include/configs/origen.h b/include/configs/origen.h
> new file mode 100644
> index 0000000..3cd9bfe
> --- /dev/null
> +++ b/include/configs/origen.h
...
> +#define COPY_BL2_SIZE		0x80000
> +#define BL2_START_OFFSET	((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
> +#define BL2_SIZE_BLOC_COUNT	(COPY_BL2_SIZE/512)

Some of the defines in this file are not used anywhere in the code
(for example, COPY_BL2_SIZE, COPY_BL2_SIZEBL2_START_OFFSET or
BL2_SIZE_BLOC_COUNT.  Please remove unused defines from this patch.

Best regards,

Wolfgang Denk
Chander Kashyap Aug. 3, 2011, 3:47 a.m. | #2
Dear Wolfgang Denk,

On 31 July 2011 15:30, Wolfgang Denk <wd@denx.de> wrote:

> Dear Chander Kashyap,
>
> In message <1311914519-10531-2-git-send-email-chander.kashyap@linaro.org>
> you wrote:
> > Origen board is based upon S5PV310 SoC which is similiar to
> > S5PC210 SoC.
> >
> > Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
> ...
> > +     /* APLL(1), MPLL(1), CORE(0), HPM(0) */
> > +     ldr     r1, =0x0101
> > +     ldr     r2, =0x14200                    @CLK_SRC_CPU
> ...
> > +     mov     r1, #0x10000
> ...
> > +     ldr     r1, =0x00
> > +     ldr     r2, =0x0C210                    @CLK_SRC_TOP0
> ...
> > +     ldr     r1, =0x00
> > +     ldr     r2, =0x0C214                    @CLK_SRC_TOP1_OFFSET
> ...
> > +     ldr     r1, =0x10000
> > +     ldr     r2, =0x10200                    @CLK_SRC_DMC_OFFSET
> ...
>
> ..
> > +     /*
> > +      * CLK_DIV_DMC0:
> > +      *
> > +      * CORE_TIMERS_RATIO[28]        0x1
> > +      * COPY2_RATIO[24]              0x3
> > +      * DMCP_RATIO[20]               0x1
> > +      * DMCD_RATIO[16]               0x1
> > +      * DMC_RATIO[12]                0x1
> > +      * DPHY_RATIO[8]                0x1
> > +      * ACP_PCLK_RATIO[4]            0x1
> > +      * ACP_RATIO[0]                 0x3
> > +      */
> > +     ldr     r1, =0x13111113
> > +     ldr     r2, =0x010500                   @CLK_DIV_DMC0_OFFSET
> > +     str     r1, [r0, r2]
>
>
> lease get rid of all these magic hard coded constants.  Use symbolic
> names instead. If needed, auto-generate these from the respective C
> structs.  If needed, create the C structs.
>

I will change hard coded values to  symbolic names.

>
> ...
> > --- /dev/null
> > +++ b/board/samsung/origen/mem_setup.S
> > @@ -0,0 +1,359 @@
>
> What exactly is the reeason for not coding this in C ?
>
> ...
> > +#ifdef CONFIG_MIU_1BIT_12_INTERLEAVED
> > +     ldr     r1, =0x0000000c
> > +     str     r1, [r0, #0x400]
> > +     ldr     r1, =0x00000001
> > +     str     r1, [r0, #0xc00]
> > +#elif defined(CONFIG_MIU_1BIT_7_INTERLEAVED)
> > +     ldr     r1, =0x00000007
> > +     str     r1, [r0, #0x400]
> > +     ldr     r1, =0x00000001
> > +     str     r1, [r0, #0xc00]
> > +#elif defined(CONFIG_MIU_2BIT_21_12_INTERLEAVED)
> > +     ldr     r1, =0x2000150c
> > +     str     r1, [r0, #0x400]
> > +     ldr     r1, =0x00000001
> > +     str     r1, [r0, #0xc00]
> > +#elif defined(CONFIG_MIU_2BIT_21_7_INTERLEAVED)
> > +     ldr     r1, =0x20001507
> > +     str     r1, [r0, #0x400]
> > +     ldr     r1, =0x00000001
> > +     str     r1, [r0, #0xc00]
> > +#elif defined(CONFIG_MIU_2BIT_31_INTERLEAVED)
> > +     ldr     r1, =0x0000001d
> > +     str     r1, [r0, #0x400]
> > +     ldr     r1, =0x00000001
> > +     str     r1, [r0, #0xc00]
>
> See above.  Please get rid of all these hard-ciooded magic numbers.
> [Eventually this happens automativcally when you rewrite this in C.]

I will use symbolic names.

>
> > +int dram_init(void)
> > +{
> > +     gd->ram_size    = get_ram_size((long *)PHYS_SDRAM_1,
> PHYS_SDRAM_1_SIZE)
> > +                     + get_ram_size((long *)PHYS_SDRAM_2,
> PHYS_SDRAM_2_SIZE)
> > +                     + get_ram_size((long *)PHYS_SDRAM_3,
> PHYS_SDRAM_3_SIZE)
> > +                     + get_ram_size((long *)PHYS_SDRAM_4,
> PHYS_SDRAM_4_SIZE);
> > +
> > +     return 0;
> > +}
> > +
> > +void dram_init_banksize(void)
> > +{
> > +     gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> > +     gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> > +     gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
> > +     gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
> > +     gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
> > +     gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
> > +     gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
> > +     gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
> > +}
>
> How do you detect memory issues in one of the memory banks, say, a
> memory error in bank 3?
>
 get_ram_size will take care for it.


> > diff --git a/include/configs/origen.h b/include/configs/origen.h
> > new file mode 100644
> > index 0000000..3cd9bfe
> > --- /dev/null
> > +++ b/include/configs/origen.h
> ...
> > +#define COPY_BL2_SIZE                0x80000
> > +#define BL2_START_OFFSET     ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
> > +#define BL2_SIZE_BLOC_COUNT  (COPY_BL2_SIZE/512)
>
> Some of the defines in this file are not used anywhere in the code
> (for example, COPY_BL2_SIZE, COPY_BL2_SIZEBL2_START_OFFSET or
> BL2_SIZE_BLOC_COUNT.  Please remove unused defines from this patch.
>
> These are used in spl code. I will move them to spl patch.


> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
> Don't hit a man when he's down - kick him; it's easier.
>
Wolfgang Denk Aug. 3, 2011, 5:59 a.m. | #3
Dear Chander Kashyap,

In message <CANuQgHFVBv-b5ecRqkrkcpPOwx2umpBR_RFPRx-c0fbvLmxNxQ@mail.gmail.com> you wrote:
> 
> > > +void dram_init_banksize(void)
> > > +{
> > > +     gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> > > +     gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> > > +     gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
> > > +     gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
> > > +     gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
> > > +     gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
> > > +     gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
> > > +     gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
> > > +}
> >
> > How do you detect memory issues in one of the memory banks, say, a
> > memory error in bank 3?
> >
>  get_ram_size will take care for it.

How so?  You are setting these to fixed, predefined values.

If get_ram_size() for bank 3 returns a size of 0, you will still set
the size to PHYS_SDRAM_3_SIZE here.


Best regards,

Wolfgang Denk
Chander Kashyap Aug. 3, 2011, 7:24 a.m. | #4
On 3 August 2011 11:29, Wolfgang Denk <wd@denx.de> wrote:

> Dear Chander Kashyap,
>
> In message <
> CANuQgHFVBv-b5ecRqkrkcpPOwx2umpBR_RFPRx-c0fbvLmxNxQ@mail.gmail.com> you
> wrote:
> >
> > > > +void dram_init_banksize(void)
> > > > +{
> > > > +     gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> > > > +     gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> > > > +     gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
> > > > +     gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
> > > > +     gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
> > > > +     gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
> > > > +     gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
> > > > +     gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
> > > > +}
> > >
> > > How do you detect memory issues in one of the memory banks, say, a
> > > memory error in bank 3?
> > >
> >  get_ram_size will take care for it.
>
> How so?  You are setting these to fixed, predefined values.
>
> If get_ram_size() for bank 3 returns a size of 0, you will still set
> the size to PHYS_SDRAM_3_SIZE here.
>
Ah. I got yours point. I will rectify it.

>
>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
> 1000 pains                                              = 1 Megahertz
>
Chander Kashyap Aug. 9, 2011, 10:32 a.m. | #5
Dear Wolfgang Denk,

On 3 August 2011 09:17, Chander Kashyap <chander.kashyap@linaro.org> wrote:

> Dear Wolfgang Denk,
>
> On 31 July 2011 15:30, Wolfgang Denk <wd@denx.de> wrote:
>
>> Dear Chander Kashyap,
>>
>> In message <1311914519-10531-2-git-send-email-chander.kashyap@linaro.org>
>> you wrote:
>> > Origen board is based upon S5PV310 SoC which is similiar to
>> > S5PC210 SoC.
>> >
>> > Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
>> ...
>> > +     /* APLL(1), MPLL(1), CORE(0), HPM(0) */
>> > +     ldr     r1, =0x0101
>> > +     ldr     r2, =0x14200                    @CLK_SRC_CPU
>> ...
>> > +     mov     r1, #0x10000
>> ...
>> > +     ldr     r1, =0x00
>> > +     ldr     r2, =0x0C210                    @CLK_SRC_TOP0
>> ...
>> > +     ldr     r1, =0x00
>> > +     ldr     r2, =0x0C214                    @CLK_SRC_TOP1_OFFSET
>> ...
>> > +     ldr     r1, =0x10000
>> > +     ldr     r2, =0x10200                    @CLK_SRC_DMC_OFFSET
>> ...
>>
>> ..
>> > +     /*
>> > +      * CLK_DIV_DMC0:
>> > +      *
>> > +      * CORE_TIMERS_RATIO[28]        0x1
>> > +      * COPY2_RATIO[24]              0x3
>> > +      * DMCP_RATIO[20]               0x1
>> > +      * DMCD_RATIO[16]               0x1
>> > +      * DMC_RATIO[12]                0x1
>> > +      * DPHY_RATIO[8]                0x1
>> > +      * ACP_PCLK_RATIO[4]            0x1
>> > +      * ACP_RATIO[0]                 0x3
>> > +      */
>> > +     ldr     r1, =0x13111113
>> > +     ldr     r2, =0x010500                   @CLK_DIV_DMC0_OFFSET
>> > +     str     r1, [r0, r2]
>>
>>
>> lease get rid of all these magic hard coded constants.  Use symbolic
>> names instead. If needed, auto-generate these from the respective C
>> structs.  If needed, create the C structs.
>>
>
> I will change hard coded values to  symbolic names
>

While doing this, I find that the values written to the registers are used
just once. So do you still prefer to have them as macros ? I did convert the
register offsets and addresses to macros, but did not find it right to have
macros for register values that are used just once. Please advise.


>> ...
>> > --- /dev/null
>> > +++ b/board/samsung/origen/mem_setup.S
>> > @@ -0,0 +1,359 @@
>>
>> What exactly is the reeason for not coding this in C ?
>>
>> ...
>> > +#ifdef CONFIG_MIU_1BIT_12_INTERLEAVED
>> > +     ldr     r1, =0x0000000c
>> > +     str     r1, [r0, #0x400]
>> > +     ldr     r1, =0x00000001
>> > +     str     r1, [r0, #0xc00]
>> > +#elif defined(CONFIG_MIU_1BIT_7_INTERLEAVED)
>> > +     ldr     r1, =0x00000007
>> > +     str     r1, [r0, #0x400]
>> > +     ldr     r1, =0x00000001
>> > +     str     r1, [r0, #0xc00]
>> > +#elif defined(CONFIG_MIU_2BIT_21_12_INTERLEAVED)
>> > +     ldr     r1, =0x2000150c
>> > +     str     r1, [r0, #0x400]
>> > +     ldr     r1, =0x00000001
>> > +     str     r1, [r0, #0xc00]
>> > +#elif defined(CONFIG_MIU_2BIT_21_7_INTERLEAVED)
>> > +     ldr     r1, =0x20001507
>> > +     str     r1, [r0, #0x400]
>> > +     ldr     r1, =0x00000001
>> > +     str     r1, [r0, #0xc00]
>> > +#elif defined(CONFIG_MIU_2BIT_31_INTERLEAVED)
>> > +     ldr     r1, =0x0000001d
>> > +     str     r1, [r0, #0x400]
>> > +     ldr     r1, =0x00000001
>> > +     str     r1, [r0, #0xc00]
>>
>> See above.  Please get rid of all these hard-ciooded magic numbers.
>> [Eventually this happens automativcally when you rewrite this in C.]
>
> I will use symbolic names.
>
>>
>> > +int dram_init(void)
>> > +{
>> > +     gd->ram_size    = get_ram_size((long *)PHYS_SDRAM_1,
>> PHYS_SDRAM_1_SIZE)
>> > +                     + get_ram_size((long *)PHYS_SDRAM_2,
>> PHYS_SDRAM_2_SIZE)
>> > +                     + get_ram_size((long *)PHYS_SDRAM_3,
>> PHYS_SDRAM_3_SIZE)
>> > +                     + get_ram_size((long *)PHYS_SDRAM_4,
>> PHYS_SDRAM_4_SIZE);
>> > +
>> > +     return 0;
>> > +}
>> > +
>> > +void dram_init_banksize(void)
>> > +{
>> > +     gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
>> > +     gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
>> > +     gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
>> > +     gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
>> > +     gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
>> > +     gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
>> > +     gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
>> > +     gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
>> > +}
>>
>> How do you detect memory issues in one of the memory banks, say, a
>> memory error in bank 3?
>>
>  get_ram_size will take care for it.
>
>
>> > diff --git a/include/configs/origen.h b/include/configs/origen.h
>> > new file mode 100644
>> > index 0000000..3cd9bfe
>> > --- /dev/null
>> > +++ b/include/configs/origen.h
>> ...
>> > +#define COPY_BL2_SIZE                0x80000
>> > +#define BL2_START_OFFSET     ((CONFIG_ENV_OFFSET +
>> CONFIG_ENV_SIZE)/512)
>> > +#define BL2_SIZE_BLOC_COUNT  (COPY_BL2_SIZE/512)
>>
>> Some of the defines in this file are not used anywhere in the code
>> (for example, COPY_BL2_SIZE, COPY_BL2_SIZEBL2_START_OFFSET or
>> BL2_SIZE_BLOC_COUNT.  Please remove unused defines from this patch.
>>
>> These are used in spl code. I will move them to spl patch.
>
>
>> Best regards,
>>
>> Wolfgang Denk
>>
>> --
>> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
>> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
>> Don't hit a man when he's down - kick him; it's easier.
>>
>
>
>
> --
> with warm regards,
> Chander Kashyap
>
Detlev Zundel Aug. 10, 2011, 10:18 a.m. | #6
Hi Chander,

[...]

>>> lease get rid of all these magic hard coded constants.  Use symbolic
>>> names instead. If needed, auto-generate these from the respective C
>>> structs.  If needed, create the C structs.
>>>
>>
>> I will change hard coded values to  symbolic names
>>
>
> While doing this, I find that the values written to the registers are used
> just once. So do you still prefer to have them as macros ? I did convert the
> register offsets and addresses to macros, but did not find it right to have
> macros for register values that are used just once. Please advise.

Most of all we want to get rid of address constants in code.  For
_values_ that are written to some register, my personal preference is
not so strong, alas if you _do_ use macros, usually already the macro
name carries documentation as to what this is and it will make code
reuse easier for the people having to maintain or build upon your code
in the future.

Cheers
  Detlev
Chander Kashyap Aug. 11, 2011, 4:17 a.m. | #7
Hi  Detlev,

On 10 August 2011 15:48, Detlev Zundel <dzu@denx.de> wrote:

> Hi Chander,
>
> [...]
>
> >>> lease get rid of all these magic hard coded constants.  Use symbolic
> >>> names instead. If needed, auto-generate these from the respective C
> >>> structs.  If needed, create the C structs.
> >>>
> >>
> >> I will change hard coded values to  symbolic names
> >>
> >
> > While doing this, I find that the values written to the registers are
> used
> > just once. So do you still prefer to have them as macros ? I did convert
> the
> > register offsets and addresses to macros, but did not find it right to
> have
> > macros for register values that are used just once. Please advise.
>
> Most of all we want to get rid of address constants in code.  For
> _values_ that are written to some register, my personal preference is
> not so strong, alas if you _do_ use macros, usually already the macro
> name carries documentation as to what this is and it will make code
> reuse easier for the people having to maintain or build upon your code
> in the future.
>

Thanks for the inputs.

>
> Cheers
>  Detlev
>
> --
> Zivilisation ist der Zaubertrick, der uns unsere wahre Natur verbirgt.
>                                            -- Salman Rushdie
> --
> DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu@denx.de
>

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 6e6affa..8526642 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -709,6 +709,7 @@  Minkyu Kang <mk7.kang@samsung.com>
 
 Chander Kashyap <k.chander@samsung.com>
 
+	origen			ARM ARMV7 (S5PC210 SoC)
 	SMDKV310		ARM ARMV7 (S5PC210 SoC)
 
 Torsten Koschorrek <koschorrek@synertronixx.de>
diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile
new file mode 100644
index 0000000..65eff91
--- /dev/null
+++ b/board/samsung/origen/Makefile
@@ -0,0 +1,46 @@ 
+#
+# Copyright (C) 2011 Samsung Electronics
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+SOBJS	:= mem_setup.o
+SOBJS	+= lowlevel_init.o
+COBJS	+= origen.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	 $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S
new file mode 100644
index 0000000..4f9d4ff
--- /dev/null
+++ b/board/samsung/origen/lowlevel_init.S
@@ -0,0 +1,464 @@ 
+/*
+ * Lowlevel setup for ORIGEN board based on S5PV310
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ * r7 has GPIO part1 base 0x11400000
+ * r6 has GPIO part2 base 0x11000000
+ */
+
+#define MEM_DLLl_ON
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE
+
+	.globl lowlevel_init
+lowlevel_init:
+	push	{lr}
+
+	/* r5 has always zero */
+	mov	r5, #0
+	ldr	r7, =S5PC210_GPIO_PART1_BASE
+	ldr	r6, =S5PC210_GPIO_PART2_BASE
+
+	/* check reset status  */
+	ldr     r0, =(S5PC210_POWER_BASE + 0x804)	@ INFORM1
+	ldr     r1, [r0]
+
+	/* AFTR wakeup reset */
+	ldr	r2, =S5P_CHECK_DIDLE
+	cmp	r1, r2
+	beq	exit_wakeup
+
+	/* Sleep wakeup reset */
+	ldr	r2, =S5P_CHECK_SLEEP
+	cmp	r1, r2
+	beq	wakeup_reset
+
+	/*
+	 * If U-boot is already running in ram, no need to relocate U-Boot.
+	 * Memory controller must be configured before relocating U-Boot
+	 * in ram.
+	 */
+	ldr	r0, =0x0ffffff		/* r0 <- Mask Bits*/
+	bic	r1, pc, r0		/* pc <- current addr of code */
+					/* r1 <- unmasked bits of pc */
+	ldr	r2, _TEXT_BASE		/* r2 <- original base addr in ram */
+	bic	r2, r2, r0		/* r2 <- unmasked bits of r2*/
+	cmp     r1, r2                  /* compare r1, r2 */
+	beq     1f			/* r0 == r1 then skip sdram init */
+
+	/* init system clock */
+	bl system_clock_init
+
+	/* Memory initialize */
+	bl mem_ctrl_asm_init
+
+1:
+	/* for UART */
+	bl uart_asm_init
+	bl tzpc_init
+	pop	{pc}
+
+wakeup_reset:
+	bl system_clock_init
+	bl mem_ctrl_asm_init
+	bl tzpc_init
+
+exit_wakeup:
+	/* Load return address and jump to kernel */
+	ldr     r0, =(S5PC210_POWER_BASE + 0x800)	@ INFORM0
+
+	/* r1 = physical address of s5pc210_cpu_resume function */
+	ldr	r1, [r0]
+
+	/* Jump to kernel*/
+	mov	pc, r1
+	nop
+	nop
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+	push	{lr}
+	ldr	r0, =S5PC210_CLOCK_BASE
+
+	/* APLL(1), MPLL(1), CORE(0), HPM(0) */
+	ldr	r1, =0x0101
+	ldr	r2, =0x14200			@CLK_SRC_CPU
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x10000
+2:	subs	r1, r1, #1
+	bne	2b
+
+	ldr	r1, =0x00
+	ldr	r2, =0x0C210			@CLK_SRC_TOP0
+	str	r1, [r0, r2]
+
+	ldr	r1, =0x00
+	ldr	r2, =0x0C214			@CLK_SRC_TOP1_OFFSET
+	str	r1, [r0, r2]
+
+	/* DMC */
+	ldr	r1, =0x10000
+	ldr	r2, =0x10200			@CLK_SRC_DMC_OFFSET
+	str	r1, [r0, r2]
+
+	/*CLK_SRC_LEFTBUS */
+	ldr	r1, =0x00
+	ldr	r2, =0x04200			@CLK_SRC_LEFTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	/*CLK_SRC_RIGHTBUS */
+	ldr	r1, =0x00
+	ldr	r2, =0x08200			@CLK_SRC_RIGHTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
+	ldr	r1, =0x066666
+	ldr	r2, =0x0C240			@ CLK_SRC_FSYS
+	str	r1, [r0, r2]
+
+	/* UART[0:4] */
+	ldr	r1, =0x0666666
+	ldr	r2, =0x0C250			@CLK_SRC_PERIL0_OFFSET
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x10000
+3:	subs	r1, r1, #1
+	bne	3b
+
+	/*
+	 * CLK_DIV_CPU0:
+	 *
+	 * PCLK_DBG_RATIO[20]	0x1
+	 * ATB_RATIO[16]	0x3
+	 * PERIPH_RATIO[12]	0x3
+	 * COREM1_RATIO[8]	0x7
+	 * COREM0_RATIO[4]	0x3
+	 */
+	ldr	r1, =0x0133730
+	ldr	r2, =0x14500			@CLK_DIV_CPU0_OFFSET
+	str	r1, [r0, r2]
+
+	/* CLK_DIV_CPU1: COPY_RATIO [0]	0x3 */
+	ldr	r1, =0x03
+	ldr	r2, =0x14504			@CLK_DIV_CPU1_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * CLK_DIV_DMC0:
+	 *
+	 * CORE_TIMERS_RATIO[28]	0x1
+	 * COPY2_RATIO[24]		0x3
+	 * DMCP_RATIO[20]		0x1
+	 * DMCD_RATIO[16]		0x1
+	 * DMC_RATIO[12]		0x1
+	 * DPHY_RATIO[8]		0x1
+	 * ACP_PCLK_RATIO[4]		0x1
+	 * ACP_RATIO[0]			0x3
+	 */
+	ldr	r1, =0x13111113
+	ldr	r2, =0x010500			@CLK_DIV_DMC0_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * CLK_DIV_DMC1:
+	 *
+	 * DPM_RATIO[24]	0x1
+	 * DVSEM_RATIO[16]	0x1
+	 * PWI_RATIO[8]		0x1
+	 */
+	ldr	r1, =0x01010100
+	ldr	r2, =0x010504			@CLK_DIV_DMC1_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * CLK_DIV_LEFRBUS:
+	 *
+	 * GPL_RATIO[4]		0x1
+	 * GDL_RATIO[0]		0x3
+	 */
+	ldr	r1, =0x013
+	ldr	r2, =0x04500			@CLK_DIV_LEFTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * CLK_DIV_RIGHTBUS:
+	 *
+	 * GPR_RATIO[4]		0x1
+	 * GDR_RATIO[0]		0x3
+	 */
+	ldr	r1, =0x013
+	ldr	r2, =0x08500			@CLK_DIV_RIGHTBUS_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * CLK_DIV_TOP:
+	 *
+	 * ONENAND_RATIO[16]	0x0
+	 * ACLK_133_RATIO[12]	0x5
+	 * ACLK_160_RATIO[8]	0x4
+	 * ACLK_100_RATIO[4]	0x7
+	 * ACLK_200_RATIO[0]	0x3
+	 */
+	ldr	r1, =0x05473
+	ldr	r2, =0x0C510			@CLK_DIV_TOP_OFFSET
+	str	r1, [r0, r2]
+
+	/* MMC[0:1] */
+	ldr	r1, =0x000f000f			/* 800(MPLL) / (15 + 1) */
+	ldr	r2, =0x0C544			@ CLK_DIV_FSYS1
+	str	r1, [r0, r2]
+
+	/* MMC[2:3] */
+	ldr	r1, =0x000f000f			/* 800(MPLL) / (15 + 1) */
+	ldr	r2, =0x0C548			@ CLK_DIV_FSYS2
+	str	r1, [r0, r2]
+
+	/* MMC4 */
+	ldr	r1, =0x000f			/* 800(MPLL) / (15 + 1) */
+	ldr	r2, =0x0C54C			@ CLK_DIV_FSYS3
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x10000
+4:	subs	r1, r1, #1
+	bne	4b
+
+	/*
+	 * CLK_DIV_PERIL0:
+	 *
+	 * UART5_RATIO[20]	8
+	 * UART4_RATIO[16]	8
+	 * UART3_RATIO[12]	8
+	 * UART2_RATIO[8]	8
+	 * UART1_RATIO[4]	8
+	 * UART0_RATIO[0]	8
+	 */
+	ldr	r1, =0x774777
+	ldr	r2, =0x0C550			@CLK_DIV_PERIL0_OFFSET
+	str	r1, [r0, r2]
+
+	/* Set PLL locktime */
+	ldr	r1, =0x01C20
+	ldr	r2, =0x014000			@APLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =0x01C20
+	ldr	r2, =0x014008			@MPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =0x01C20
+	ldr	r2, =0x0C010			@EPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+	ldr	r1, =0x01C20
+	ldr	r2, =0x0C020			@VPLL_LOCK_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * APLL_CON1:
+	 *
+	 * APLL_AFC_ENB[31]	0x1
+	 * APLL_AFC[0]		0xC
+	 */
+	ldr	r1, =0x8000000C
+	ldr	r2, =0x014104			@APLL_CON1_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * APLL_CON0:
+	 *
+	 * APLL_MDIV[16]	0xFA
+	 * APLL_PDIV[8]		0x6
+	 * APLL_SDIV[0]		0x1
+	 */
+	ldr	r1, =0x80FA0601
+	ldr	r2, =0x014100			@APLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * MPLL_CON1:
+	 *
+	 * MPLL_AFC_ENB[31]	0x1
+	 * MPLL_AFC[0]		0x1C
+	 */
+	ldr	r1, =0x0000001C
+	ldr	r2, =0x01410C			@MPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * MPLL_CON0:
+	 *
+	 * MPLL_MDIV[16]	0xC8
+	 * MPLL_PDIV[8]		0x6
+	 * MPLL_SDIV[0]		0x1
+	 */
+	ldr	r1, =0x80C80601
+	ldr	r2, =0x014108			@MPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/* EPLL */
+	ldr	r1, =0x0
+	ldr	r2, =0x0C114			@EPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * EPLL_CON0:
+	 *
+	 * EPLL_MDIV[16]	0x30
+	 * EPLL_PDIV[8]		0x3
+	 * EPLL_SDIV[0]		0x2
+	 */
+	ldr	r1, =0x80300302
+	ldr	r2, =0x0C110			@EPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * VPLL_CON1:
+	 *
+	 * VPLL_MRR[24]		0x11
+	 * VPLL_MFR[16]		0x0
+	 * VPLL_K[0]		0x400
+	 */
+	ldr	r1, =0x11000400
+	ldr	r2, =0x0C124			@VPLL_CON1_OFFSET
+	str	r1, [r0, r2]
+
+	/*
+	 * VPLL_CON0:
+	 *
+	 * VPLL_MDIV[16]	0x35
+	 * VPLL_PDIV[8]		0x3
+	 * VPLL_SDIV[0]		0x2
+	 */
+	ldr	r1, =0x80350302
+	ldr	r2, =0x0C120			@VPLL_CON0_OFFSET
+	str	r1, [r0, r2]
+
+	/* wait ?us */
+	mov	r1, #0x30000
+3:	subs	r1, r1, #1
+	bne	3b
+
+	pop	{pc}
+/*
+ * uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
+ * void uart_asm_init(void)
+ */
+	.globl uart_asm_init
+uart_asm_init:
+
+	/* setup UART0-UART3 GPIOs (part1) */
+	mov	r0, r7
+	ldr	r1, =0x22222222
+	str	r1, [r0, #0x00]			@ S5PC210_GPIO_A0_OFFSET
+	ldr	r1, =0x00222222
+	str	r1, [r0, #0x20]			@ S5PC210_GPIO_A1_OFFSET
+
+	ldr r0, =S5PC210_UART_BASE
+	add r0, r0, #S5PC210_DEFAULT_UART_OFFSET
+
+	ldr	r1, =0x3C5
+	str	r1, [r0, #0x4]
+	ldr	r1, =0x111
+	str	r1, [r0, #0x8]
+	ldr	r1, =0x3
+	str	r1, [r0, #0x0]
+	ldr	r1, =0x35
+	str	r1, [r0, #0x28]
+	ldr	r1, =0x4
+	str	r1, [r0, #0x2c]
+
+	mov	pc, lr
+	nop
+	nop
+	nop
+
+/* Setting TZPC[TrustZone Protection Controller] */
+tzpc_init:
+	ldr	r0, =0x10110000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	ldr	r0, =0x10120000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	ldr	r0, =0x10130000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	ldr	r0, =0x10140000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	ldr	r0, =0x10150000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	ldr	r0, =0x10160000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x0804]
+	str	r1, [r0, #0x0810]
+	str	r1, [r0, #0x081C]
+	str	r1, [r0, #0x0828]
+
+	mov	pc, lr
diff --git a/board/samsung/origen/mem_setup.S b/board/samsung/origen/mem_setup.S
new file mode 100644
index 0000000..22d8f39
--- /dev/null
+++ b/board/samsung/origen/mem_setup.S
@@ -0,0 +1,359 @@ 
+/*
+ * Memory setup for ORIGEN board based on S5PV310
+ *
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+#define SET_MIU
+
+#define MEM_DLL
+
+#ifdef CONFIG_CLK_800_330_165
+#define DRAM_CLK_330
+#elif defined(CONFIG_CLK_1000_200_200)
+#define DRAM_CLK_200
+#elif defined(CONFIG_CLK_1000_330_165)
+#define DRAM_CLK_330
+#elif defined(CONFIG_CLK_800_400_200) || defined(CONFIG_CLK_1000_400_200)
+#define DRAM_CLK_400
+#else
+#error "CONFIG_CLK_XXX not defined"
+#endif
+
+	.globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+
+	/*
+	* Async bridge configuration at CPU_core:
+	* 1: half_sync
+	* 0: full_sync
+	*/
+	ldr r0, =0x10010350
+	mov r1, #1
+	str r1, [r0]
+
+#ifdef SET_MIU
+	ldr	r0, =S5PC210_MIU_BASE	@0x10600000
+
+#ifdef CONFIG_MIU_1BIT_12_INTERLEAVED
+	ldr	r1, =0x0000000c
+	str	r1, [r0, #0x400]
+	ldr	r1, =0x00000001
+	str	r1, [r0, #0xc00]
+#elif defined(CONFIG_MIU_1BIT_7_INTERLEAVED)
+	ldr	r1, =0x00000007
+	str	r1, [r0, #0x400]
+	ldr	r1, =0x00000001
+	str	r1, [r0, #0xc00]
+#elif defined(CONFIG_MIU_2BIT_21_12_INTERLEAVED)
+	ldr	r1, =0x2000150c
+	str	r1, [r0, #0x400]
+	ldr	r1, =0x00000001
+	str	r1, [r0, #0xc00]
+#elif defined(CONFIG_MIU_2BIT_21_7_INTERLEAVED)
+	ldr	r1, =0x20001507
+	str	r1, [r0, #0x400]
+	ldr	r1, =0x00000001
+	str	r1, [r0, #0xc00]
+#elif defined(CONFIG_MIU_2BIT_31_INTERLEAVED)
+	ldr	r1, =0x0000001d
+	str	r1, [r0, #0x400]
+	ldr	r1, =0x00000001
+	str	r1, [r0, #0xc00]
+#endif
+#endif
+	/* DREX0 */
+	ldr	r0, =S5PC210_DMC0_BASE	@0x10400000
+
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0xE3855703
+	str	r1, [r0, #0x44]		@DMC_PHYZQCONTROL
+
+	mov	r2, #0x100000
+1:	subs	r2, r2, #1
+	bne	1b
+
+	ldr	r1, =0xe000008e
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0x71101008
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+	ldr	r1, =0x7110100A
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+	ldr	r1, =0x7110100B
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+
+	ldr	r1, =0x00000000
+	str	r1, [r0, #0x20]		@DMC_PHYCONTROL2
+
+	ldr	r1, =0x0FFF301a
+	str	r1, [r0, #0x00]		@DMC_CONCONTROL
+	ldr	r1, =0x00312640
+	str	r1, [r0, #0x04]		@DMC_MEMCONTROL]
+
+#ifdef CONFIG_MIU_LINEAR
+	ldr	r1, =0x40e01323
+	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
+	ldr	r1, =0x60e01323
+	str	r1, [r0, #0x0C]		@DMC_MEMCONFIG1
+#else	/* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
+	ldr	r1, =0x20e01323
+	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
+	ldr	r1, =0x40e01323
+	str	r1, [r0, #0x0C]		@DMC_MEMCONFIG1
+#endif
+
+	ldr	r1, =0xff000000
+	str	r1, [r0, #0x14]		@DMC_PRECHCONFIG
+
+	ldr	r1, =0x000000BB
+	str	r1, [r0, #0x30]		@DMC_TIMINGAREF
+
+#ifdef DRAM_CLK_330
+	ldr	r1, =0x3545548d
+	str	r1, [r0, #0x34]		@DMC_TIMINGROW
+	ldr	r1, =0x45430506
+	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
+	ldr	r1, =0x46000A3C
+	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
+#endif
+#ifdef DRAM_CLK_400
+	ldr	r1, =0x4046654f
+	str	r1, [r0, #0x34]		@DMC_TIMINGROW
+	ldr	r1, =0x46400506
+	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
+	ldr	r1, =0x52000A3C
+	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
+#endif
+	ldr	r1, =0x07000000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+2:	subs	r2, r2, #1
+	bne	2b
+
+	ldr	r1, =0x00020000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00030000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00010002
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00000328
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+3:	subs	r2, r2, #1
+	bne	3b
+
+	ldr	r1, =0x0a000000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+4:	subs	r2, r2, #1
+	bne	4b
+
+	ldr	r1, =0x07100000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+5:	subs	r2, r2, #1
+	bne	5b
+
+	ldr	r1, =0x00120000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00130000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00110002
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00100328
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+6:	subs	r2, r2, #1
+	bne	6b
+
+	ldr	r1, =0x0a100000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+7:	subs	r2, r2, #1
+	bne	7b
+
+	ldr	r1, =0xe000008e
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	mov	r2, #0x100000
+8:	subs	r2, r2, #1
+	bne	8b
+
+	/* DREX1 */
+	ldr	r0, =S5PC210_DMC1_BASE	@0x10410000
+
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0xE3855703
+	str	r1, [r0, #0x44]		@DMC_PHYZQCONTROL
+
+	mov	r2, #0x100000
+1:	subs	r2, r2, #1
+	bne	1b
+
+	ldr	r1, =0xe000008e
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	ldr	r1, =0x71101008
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+	ldr	r1, =0x7110100A
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+	ldr	r1, =0x7110100B
+	str	r1, [r0, #0x18]		@DMC_PHYCONTROL0
+
+	ldr	r1, =0x00000000
+	str	r1, [r0, #0x20]		@DMC_PHYCONTROL2
+
+	ldr	r1, =0x0FFF301a
+	str	r1, [r0, #0x00]		@DMC_CONCONTROL
+	ldr	r1, =0x00312640
+	str	r1, [r0, #0x04]		@DMC_MEMCONTROL]
+
+#ifdef CONFIG_MIU_LINEAR
+	ldr	r1, =0x40e01323
+	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
+	ldr	r1, =0x60e01323
+	str	r1, [r0, #0x0C]		@DMC_MEMCONFIG1
+#else	/* @MIU_1BIT_INTERLEAVED | MIU_2BIT_INTERLEAVED */
+	ldr	r1, =0x20e01323
+	str	r1, [r0, #0x08]		@DMC_MEMCONFIG0
+	ldr	r1, =0x40e01323
+	str	r1, [r0, #0x0C]		@DMC_MEMCONFIG1
+#endif
+
+	ldr	r1, =0xff000000
+	str	r1, [r0, #0x14]		@DMC_PRECHCONFIG
+
+	ldr	r1, =0x000000BB
+	str	r1, [r0, #0x30]		@DMC_TIMINGAREF
+
+#ifdef DRAM_CLK_330
+	ldr	r1, =0x3545548d
+	str	r1, [r0, #0x34]		@DMC_TIMINGROW
+	ldr	r1, =0x45430506
+	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
+	ldr	r1, =0x46000A3C
+	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
+#endif
+#ifdef DRAM_CLK_400
+	ldr	r1, =0x4046654f
+	str	r1, [r0, #0x34]		@DMC_TIMINGROW
+	ldr	r1, =0x46400506
+	str	r1, [r0, #0x38]		@DMC_TIMINGDATA
+	ldr	r1, =0x52000A3C
+	str	r1, [r0, #0x3C]		@DMC_TIMINGPOWER
+#endif
+
+	ldr	r1, =0x07000000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+2:	subs	r2, r2, #1
+	bne	2b
+
+	ldr	r1, =0x00020000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00030000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00010002
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00000328
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+3:	subs	r2, r2, #1
+	bne	3b
+
+	ldr	r1, =0x0a000000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+4:	subs	r2, r2, #1
+	bne	4b
+
+	ldr	r1, =0x07100000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+5:	subs	r2, r2, #1
+	bne	5b
+
+	ldr	r1, =0x00120000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00130000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00110002
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+	ldr	r1, =0x00100328
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+6:	subs	r2, r2, #1
+	bne	6b
+
+	ldr	r1, =0x0a100000
+	str	r1, [r0, #0x10]		@DMC_DIRECTCMD
+
+	mov	r2, #0x100000
+7:	subs	r2, r2, #1
+	bne	7b
+
+	ldr	r1, =0xe000008e
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+	ldr	r1, =0xe0000086
+	str	r1, [r0, #0x1C]		@DMC_PHYCONTROL1
+
+	mov	r2, #0x100000
+8:	subs	r2, r2, #1
+	bne	8b
+
+	/* turn on DREX0, DREX1 */
+	ldr	r0, =0x10400000		@APB_DMC_0_BASE
+	ldr	r1, =0x0FFF303a
+	str	r1, [r0, #0x00]		@DMC_CONCONTROL
+
+	ldr	r0, =0x10410000		@APB_DMC_1_BASE
+	ldr	r1, =0x0FFF303a
+	str	r1, [r0, #0x00]		@DMC_CONCONTROL
+
+	mov	pc, lr
diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c
new file mode 100644
index 0000000..63c827c
--- /dev/null
+++ b/board/samsung/origen/origen.c
@@ -0,0 +1,105 @@ 
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+struct s5pc210_gpio_part1 *gpio1;
+struct s5pc210_gpio_part2 *gpio2;
+
+int board_init(void)
+{
+	gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
+	gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
+
+	gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size	= get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
+			+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
+
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	printf("\nBoard: ORIGEN\n");
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	int i, err;
+
+	/*
+	 * MMC2 SD card GPIO:
+	 *
+	 * GPK2[0]	SD_2_CLK(2)
+	 * GPK2[1]	SD_2_CMD(2)
+	 * GPK2[2]	SD_2_CDn
+	 * GPK2[3:6]	SD_2_DATA[0:3](2)
+	 */
+	for (i = 0; i < 7; i++) {
+		/* GPK2[0:6] special function 2 */
+		s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2));
+
+		/* GPK2[0:6] drv 4x */
+		s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
+
+		/* GPK2[0:1] pull disable */
+		if (i == 0 || i == 1) {
+			s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
+			continue;
+		}
+
+		/* GPK2[2:6] pull up */
+		s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP);
+	}
+
+	err = s5p_mmc_init(2, 4);
+	return err;
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index 5cfaa78..1009f1c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -165,6 +165,7 @@  omap4_panda                  arm         armv7       panda               ti
 omap4_sdp4430                arm         armv7       sdp4430             ti             omap4
 s5p_goni                     arm         armv7       goni                samsung        s5pc1xx
 smdkc100                     arm         armv7       smdkc100            samsung        s5pc1xx
+origen			     arm	 armv7	     origen		 samsung	s5pc2xx
 s5pc210_universal            arm         armv7       universal_c210      samsung        s5pc2xx
 smdkv310		     arm	 armv7	     smdkv310		 samsung	s5pc2xx
 harmony                      arm         armv7       harmony             nvidia         tegra2
diff --git a/include/configs/origen.h b/include/configs/origen.h
new file mode 100644
index 0000000..3cd9bfe
--- /dev/null
+++ b/include/configs/origen.h
@@ -0,0 +1,166 @@ 
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG ORIGEN (S5PV310) board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_ARMV7			1	/*This is an ARM V7 CPU core */
+#define CONFIG_SAMSUNG			1	/* in a SAMSUNG core */
+#define CONFIG_S5P			1	/* S5P Family */
+#define CONFIG_S5PC210			1	/* which is in a S5PC210 SoC */
+#define CONFIG_ORIGEN			1	/* working with ORIGEN*/
+#define CONFIG_EVT1			1	/* EVT1 */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_L2_OFF			1
+#define CONFIG_SYS_DCACHE_OFF		1
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_TEXT_BASE		0x43E00000
+
+/* input clock of PLL: ORIGEN has 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ		24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/* MACH_TYPE_ORIGEN macro will be removed once added to mach-types */
+#define MACH_TYPE_ORIGEN		3455
+#define CONFIG_MACH_TYPE		MACH_TYPE_ORIGEN
+
+#define S5P_CHECK_SLEEP			0x00000BAD
+#define S5P_CHECK_DIDLE			0xBAD00000
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+
+/* select serial console configuration */
+#define CONFIG_SERIAL_MULTI		1
+#define CONFIG_SERIAL2			1	/* use SERIAL 1 */
+#define CONFIG_BAUDRATE			115200
+#define S5PC210_DEFAULT_UART_OFFSET	0x020000
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_MMC			1
+#define CONFIG_S5P_MMC			1
+
+/* PWM */
+#define CONFIG_PWM			1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_MMC_U_BOOT
+
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0 40007000 uImage; bootm 40007000"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"ORIGEN # "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size*/
+#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x6000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_SYS_HZ			1000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* Stack sizes */
+#define CONFIG_STACKSIZE		(256 << 10)	/* 256KB */
+
+/* ORIGEN has 4 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS	4
+#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH		1
+#undef	CONFIG_CMD_IMLS
+#define CONFIG_IDENT_STRING		" for ORIGEN"
+
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
+#endif
+
+#define CONFIG_CLK_1000_400_200
+
+/* MIU (Memory Interleaving Unit) */
+#define CONFIG_MIU_2BIT_21_7_INTERLEAVED
+
+#define CONFIG_ENV_IS_IN_MMC		1
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KB */
+#define RESERVE_BLOCK_SIZE		(512)
+#define BL1_SIZE			(16 << 10) /*16 K reserved for BL1*/
+#define CONFIG_ENV_OFFSET		(RESERVE_BLOCK_SIZE + BL1_SIZE)
+#define CONFIG_DOS_PARTITION		1
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
+
+/* U-boot copy size from boot Media to DRAM.*/
+#define COPY_BL2_SIZE		0x80000
+#define BL2_START_OFFSET	((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
+#define BL2_SIZE_BLOC_COUNT	(COPY_BL2_SIZE/512)
+#endif	/* __CONFIG_H */