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[209.132.180.67]) by mx.google.com with ESMTP id ah1si10471911pbc.97.2014.06.16.03.27.15; Mon, 16 Jun 2014 03:27:15 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932142AbaFPK1K (ORCPT + 9 others); Mon, 16 Jun 2014 06:27:10 -0400 Received: from mail-pb0-f52.google.com ([209.85.160.52]:45185 "EHLO mail-pb0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932101AbaFPK1F (ORCPT ); Mon, 16 Jun 2014 06:27:05 -0400 Received: by mail-pb0-f52.google.com with SMTP id rq2so2275486pbb.39 for ; Mon, 16 Jun 2014 03:27:05 -0700 (PDT) X-Received: by 10.68.233.37 with SMTP id tt5mr23268231pbc.154.1402914424946; Mon, 16 Jun 2014 03:27:04 -0700 (PDT) Received: from localhost.localdomain ([14.140.216.146]) by mx.google.com with ESMTPSA id gr10sm17922046pbc.84.2014.06.16.03.27.00 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 16 Jun 2014 03:27:04 -0700 (PDT) From: Chander Kashyap To: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, daniel.lezcano@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, kgene.kim@samsung.com, tomasz.figa@gmail.com, Chander Kashyap , Chander Kashyap Subject: [Patch v7 6/6] mcpm: exynos: populate suspend and powered_up callbacks Date: Mon, 16 Jun 2014 15:56:23 +0530 Message-Id: <1402914383-20471-7-git-send-email-k.chander@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1402914383-20471-1-git-send-email-k.chander@samsung.com> References: <1402914383-20471-1-git-send-email-k.chander@samsung.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Original-Sender: linux-kernel-owner@vger.kernel.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2607:f8b0:400c:c03::22d as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=neutral (body hash did not verify) header.i=@ Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Chander Kashyap In order to support cpuidle through mcpm, suspend and powered-up callbacks are required in mcpm platform code. Hence populate the same callbacks. Signed-off-by: Chander Kashyap Signed-off-by: Chander Kashyap Reviewed-by: Tomasz Figa --- Changes in v6: None Changes in v5: 1. Add comment to address cache access while c-bit is cleared in SCLTR 2. Make exynos_powered_up static Changes in v4: None Changes in v3: 1. Removed coherency enablement after suspend failure. 2. Use generic function to poweron cpu. changes in v2: 1. Fixed typo: enynos_pmu_cpunr to exynos_pmu_cpunr arch/arm/mach-exynos/mcpm-exynos.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c index 0498d0b..fc47e68 100644 --- a/arch/arm/mach-exynos/mcpm-exynos.c +++ b/arch/arm/mach-exynos/mcpm-exynos.c @@ -258,10 +258,46 @@ static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster) return -ETIMEDOUT; /* timeout */ } +static void exynos_powered_up(void) +{ + unsigned int mpidr, cpu, cluster; + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + + arch_spin_lock(&exynos_mcpm_lock); + if (cpu_use_count[cpu][cluster] == 0) + cpu_use_count[cpu][cluster] = 1; + arch_spin_unlock(&exynos_mcpm_lock); +} + +static void exynos_suspend(u64 residency) +{ + unsigned int mpidr, cpunr; + + exynos_power_down(); + + /* + * Execution reaches here only if cpu did not power down. + * Hence roll back the changes done in exynos_power_down function. + * + * CAUTION: "This function requires the stack data to be visible through + * power down and can only be executed on processors like A15 and A7 + * that hit the cache with the C bit clear in the SCTLR register." + */ + mpidr = read_cpuid_mpidr(); + cpunr = exynos_pmu_cpunr(mpidr); + + exynos_cpu_power_up(cpunr); +} + static const struct mcpm_platform_ops exynos_power_ops = { .power_up = exynos_power_up, .power_down = exynos_power_down, .wait_for_powerdown = exynos_wait_for_powerdown, + .suspend = exynos_suspend, + .powered_up = exynos_powered_up, }; static void __init exynos_mcpm_usage_count_init(void)