| Message ID | 20201106134807.9076-1-adrian.hunter@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | mmc: sdhci-pci: Prefer SDR25 timing for High Speed mode for BYT-based Intel controllers | expand |
On Fri, 6 Nov 2020 at 14:48, Adrian Hunter <adrian.hunter@intel.com> wrote: > > A UHS setting of SDR25 can give better results for High Speed mode. > > Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> > Cc: stable@vger.kernel.org # v5.4+ > --- > drivers/mmc/host/sdhci-pci-core.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c > index 23da7f7fe093..9552708846ca 100644 > --- a/drivers/mmc/host/sdhci-pci-core.c > +++ b/drivers/mmc/host/sdhci-pci-core.c > @@ -665,6 +665,15 @@ static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, > } > } > > +static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host, > + unsigned int timing) > +{ > + /* Set UHS timing to SDR25 for High Speed mode */ > + if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS) > + timing = MMC_TIMING_UHS_SDR25; I don't quite get this. If the mmc core requests high speed mode, you override this with timing settings corresponding to UHS_SDR25, right? > + sdhci_set_uhs_signaling(host, timing); > +} > + > #define INTEL_HS400_ES_REG 0x78 > #define INTEL_HS400_ES_BIT BIT(0) > > @@ -721,7 +730,7 @@ static const struct sdhci_ops sdhci_intel_byt_ops = { > .enable_dma = sdhci_pci_enable_dma, > .set_bus_width = sdhci_set_bus_width, > .reset = sdhci_reset, > - .set_uhs_signaling = sdhci_set_uhs_signaling, > + .set_uhs_signaling = sdhci_intel_set_uhs_signaling, > .hw_reset = sdhci_pci_hw_reset, > }; > > @@ -731,7 +740,7 @@ static const struct sdhci_ops sdhci_intel_glk_ops = { > .enable_dma = sdhci_pci_enable_dma, > .set_bus_width = sdhci_set_bus_width, > .reset = sdhci_cqhci_reset, > - .set_uhs_signaling = sdhci_set_uhs_signaling, > + .set_uhs_signaling = sdhci_intel_set_uhs_signaling, > .hw_reset = sdhci_pci_hw_reset, > .irq = sdhci_cqhci_irq, > }; > -- > 2.17.1 > Kind regards Uffe
On 10/11/20 2:01 pm, Ulf Hansson wrote: > On Fri, 6 Nov 2020 at 14:48, Adrian Hunter <adrian.hunter@intel.com> wrote: >> >> A UHS setting of SDR25 can give better results for High Speed mode. >> >> Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> >> Cc: stable@vger.kernel.org # v5.4+ >> --- >> drivers/mmc/host/sdhci-pci-core.c | 13 +++++++++++-- >> 1 file changed, 11 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c >> index 23da7f7fe093..9552708846ca 100644 >> --- a/drivers/mmc/host/sdhci-pci-core.c >> +++ b/drivers/mmc/host/sdhci-pci-core.c >> @@ -665,6 +665,15 @@ static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, >> } >> } >> >> +static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host, >> + unsigned int timing) >> +{ >> + /* Set UHS timing to SDR25 for High Speed mode */ >> + if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS) >> + timing = MMC_TIMING_UHS_SDR25; > > I don't quite get this. If the mmc core requests high speed mode, you > override this with timing settings corresponding to UHS_SDR25, right? Yes. There is no setting corresponding to high speed. Currently SDHCI sets no value, which means zero which is also the setting for SDR12. There was an attempt to change this in sdhci.c but it caused problems for some drivers, so it was reverted and the change was made to sdhci-brcmstb in commit 2fefc7c5f7d16e ("mmc: sdhci-brcmstb: Fix incorrect switch to HS mode"). Several other drivers also do this. > >> + sdhci_set_uhs_signaling(host, timing); >> +} >> + >> #define INTEL_HS400_ES_REG 0x78 >> #define INTEL_HS400_ES_BIT BIT(0) >> >> @@ -721,7 +730,7 @@ static const struct sdhci_ops sdhci_intel_byt_ops = { >> .enable_dma = sdhci_pci_enable_dma, >> .set_bus_width = sdhci_set_bus_width, >> .reset = sdhci_reset, >> - .set_uhs_signaling = sdhci_set_uhs_signaling, >> + .set_uhs_signaling = sdhci_intel_set_uhs_signaling, >> .hw_reset = sdhci_pci_hw_reset, >> }; >> >> @@ -731,7 +740,7 @@ static const struct sdhci_ops sdhci_intel_glk_ops = { >> .enable_dma = sdhci_pci_enable_dma, >> .set_bus_width = sdhci_set_bus_width, >> .reset = sdhci_cqhci_reset, >> - .set_uhs_signaling = sdhci_set_uhs_signaling, >> + .set_uhs_signaling = sdhci_intel_set_uhs_signaling, >> .hw_reset = sdhci_pci_hw_reset, >> .irq = sdhci_cqhci_irq, >> }; >> -- >> 2.17.1 >> > > Kind regards > Uffe >
On 11/11/20 7:34 am, Adrian Hunter wrote: > On 10/11/20 2:01 pm, Ulf Hansson wrote: >> On Fri, 6 Nov 2020 at 14:48, Adrian Hunter <adrian.hunter@intel.com> wrote: >>> >>> A UHS setting of SDR25 can give better results for High Speed mode. >>> >>> Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> >>> Cc: stable@vger.kernel.org # v5.4+ >>> --- >>> drivers/mmc/host/sdhci-pci-core.c | 13 +++++++++++-- >>> 1 file changed, 11 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c >>> index 23da7f7fe093..9552708846ca 100644 >>> --- a/drivers/mmc/host/sdhci-pci-core.c >>> +++ b/drivers/mmc/host/sdhci-pci-core.c >>> @@ -665,6 +665,15 @@ static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, >>> } >>> } >>> >>> +static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host, >>> + unsigned int timing) >>> +{ >>> + /* Set UHS timing to SDR25 for High Speed mode */ >>> + if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS) >>> + timing = MMC_TIMING_UHS_SDR25; >> >> I don't quite get this. If the mmc core requests high speed mode, you >> override this with timing settings corresponding to UHS_SDR25, right? > > Yes. There is no setting corresponding to high speed. Currently SDHCI sets > no value, which means zero which is also the setting for SDR12. There was > an attempt to change this in sdhci.c but it caused problems for some > drivers, so it was reverted and the change was made to sdhci-brcmstb in > commit 2fefc7c5f7d16e ("mmc: sdhci-brcmstb: Fix incorrect switch to HS > mode"). Several other drivers also do this. > Send V2 with expanded commit message
diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c index 23da7f7fe093..9552708846ca 100644 --- a/drivers/mmc/host/sdhci-pci-core.c +++ b/drivers/mmc/host/sdhci-pci-core.c @@ -665,6 +665,15 @@ static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, } } +static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + /* Set UHS timing to SDR25 for High Speed mode */ + if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS) + timing = MMC_TIMING_UHS_SDR25; + sdhci_set_uhs_signaling(host, timing); +} + #define INTEL_HS400_ES_REG 0x78 #define INTEL_HS400_ES_BIT BIT(0) @@ -721,7 +730,7 @@ static const struct sdhci_ops sdhci_intel_byt_ops = { .enable_dma = sdhci_pci_enable_dma, .set_bus_width = sdhci_set_bus_width, .reset = sdhci_reset, - .set_uhs_signaling = sdhci_set_uhs_signaling, + .set_uhs_signaling = sdhci_intel_set_uhs_signaling, .hw_reset = sdhci_pci_hw_reset, }; @@ -731,7 +740,7 @@ static const struct sdhci_ops sdhci_intel_glk_ops = { .enable_dma = sdhci_pci_enable_dma, .set_bus_width = sdhci_set_bus_width, .reset = sdhci_cqhci_reset, - .set_uhs_signaling = sdhci_set_uhs_signaling, + .set_uhs_signaling = sdhci_intel_set_uhs_signaling, .hw_reset = sdhci_pci_hw_reset, .irq = sdhci_cqhci_irq, };
A UHS setting of SDR25 can give better results for High Speed mode. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org # v5.4+ --- drivers/mmc/host/sdhci-pci-core.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-)