| Message ID | 20201116174112.1833368-18-lee.jones@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | Rid W=1 warnings from GPU (non-Radeon) | expand |
On Mon, Nov 16, 2020 at 9:41 AM Lee Jones <lee.jones@linaro.org> wrote: > > Very little attempt has been made to document these functions. > > Fixes the following W=1 kernel build warning(s): > > drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c:227: warning: Function parameter or member 'ctl' not described in 'mdp5_ctl_set_encoder_state' > drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c:227: warning: Function parameter or member 'pipeline' not described in 'mdp5_ctl_set_encoder_state' > drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c:227: warning: Function parameter or member 'enabled' not described in 'mdp5_ctl_set_encoder_state' > drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c:227: warning: Excess function parameter 'enable' description in 'mdp5_ctl_set_encoder_state' > drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c:529: warning: Function parameter or member 'ctl' not described in 'mdp5_ctl_commit' > drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c:529: warning: Function parameter or member 'pipeline' not described in 'mdp5_ctl_commit' > drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c:529: warning: Function parameter or member 'flush_mask' not described in 'mdp5_ctl_commit' > drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c:529: warning: Function parameter or member 'start' not described in 'mdp5_ctl_commit' > > Cc: Rob Clark <robdclark@gmail.com> > Cc: Sean Paul <sean@poorly.run> > Cc: David Airlie <airlied@linux.ie> > Cc: Daniel Vetter <daniel@ffwll.ch> > Cc: linux-arm-msm@vger.kernel.org > Cc: dri-devel@lists.freedesktop.org > Cc: freedreno@lists.freedesktop.org > Signed-off-by: Lee Jones <lee.jones@linaro.org> > Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Thanks, this one I'll try to replace with actual doc fixes, but I'll pick up the rest (and possibly this one if I run out of time) in msm-next for v5.11 as soon as I switch back to my kernel hat (next day or two) BR, -R > --- > drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c > index 030279d7b64b7..b5c40f9773629 100644 > --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c > +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c > @@ -213,10 +213,10 @@ static void send_start_signal(struct mdp5_ctl *ctl) > spin_unlock_irqrestore(&ctl->hw_lock, flags); > } > > -/** > +/* > * mdp5_ctl_set_encoder_state() - set the encoder state > * > - * @enable: true, when encoder is ready for data streaming; false, otherwise. > + * @enabled: true, when encoder is ready for data streaming; false, otherwise. > * > * Note: > * This encoder state is needed to trigger START signal (data path kickoff). > @@ -507,7 +507,7 @@ static void fix_for_single_flush(struct mdp5_ctl *ctl, u32 *flush_mask, > } > } > > -/** > +/* > * mdp5_ctl_commit() - Register Flush > * > * The flush register is used to indicate several registers are all > -- > 2.25.1 > > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c index 030279d7b64b7..b5c40f9773629 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c @@ -213,10 +213,10 @@ static void send_start_signal(struct mdp5_ctl *ctl) spin_unlock_irqrestore(&ctl->hw_lock, flags); } -/** +/* * mdp5_ctl_set_encoder_state() - set the encoder state * - * @enable: true, when encoder is ready for data streaming; false, otherwise. + * @enabled: true, when encoder is ready for data streaming; false, otherwise. * * Note: * This encoder state is needed to trigger START signal (data path kickoff). @@ -507,7 +507,7 @@ static void fix_for_single_flush(struct mdp5_ctl *ctl, u32 *flush_mask, } } -/** +/* * mdp5_ctl_commit() - Register Flush * * The flush register is used to indicate several registers are all