| Message ID | 20201126105900.26658-14-aisheng.dong@nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: imx8: architecture improvement and adding imx8qm support | expand |
> -----Original Message----- > From: Aisheng Dong > Sent: 2020年11月26日 18:59 > To: devicetree@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org; dl-linux-imx <linux-imx@nxp.com>; > linux-mmc@vger.kernel.org; Aisheng Dong <aisheng.dong@nxp.com>; Rob > Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; > Shawn Guo <shawnguo@kernel.org>; Sascha Hauer <kernel@pengutronix.de>; > Fabio Estevam <fabio.estevam@nxp.com> > Subject: [PATCH RESEND v4 13/18] arm64: dts: imx8qm: add conn ss support > > The CONN SS of MX8QM is mostly the same as MX8QXP except it has one more > USB HSIC module support. So we can fully reuse the exist CONN SS dtsi. > Add <soc>-ss-conn.dtsi with compatible string updated according to > imx8-ss-conn.dtsi. > > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: devicetree@vger.kernel.org > Cc: Shawn Guo <shawnguo@kernel.org> > Cc: Sascha Hauer <kernel@pengutronix.de> > Cc: Fabio Estevam <fabio.estevam@nxp.com> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> > --- > ChangeLog: > v2->v3: > * no changes > v1->v2: > * change to the new two cell scu clk binding > --- > .../boot/dts/freescale/imx8qm-ss-conn.dtsi | 21 +++++++++++++++++++ > 1 file changed, 21 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi > b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi > new file mode 100644 > index 000000000000..dc47c5c80eae > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi > @@ -0,0 +1,21 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2019-2020 NXP > + * Dong Aisheng <aisheng.dong@nxp.com> > + */ > + > +&fec1 { > + compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; }; > + > +&fec2 { > + compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; }; > + > +&usdhc1 { > + compatible = "fsl,imx8qm-usdhc", "fsl,imx7d-usdhc"; }; > + > +&usdhc2 { > + compatible = "fsl,imx8qm-usdhc", "fsl,imx7d-usdhc"; }; Hi Aisheng, For usdhc1 and usdhc2, the compatible setting should be like this: compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc"; Since imx8qm also support hs400es and command queue, The usdhc IP is the same with imx8qxp. Best Regards Haibo Chen > -- > 2.23.0
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi new file mode 100644 index 000000000000..dc47c5c80eae --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019-2020 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +&fec1 { + compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; +}; + +&fec2 { + compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; +}; + +&usdhc1 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx7d-usdhc"; +}; + +&usdhc2 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx7d-usdhc"; +};
The CONN SS of MX8QM is mostly the same as MX8QXP except it has one more USB HSIC module support. So we can fully reuse the exist CONN SS dtsi. Add <soc>-ss-conn.dtsi with compatible string updated according to imx8-ss-conn.dtsi. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> --- ChangeLog: v2->v3: * no changes v1->v2: * change to the new two cell scu clk binding --- .../boot/dts/freescale/imx8qm-ss-conn.dtsi | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi