diff mbox series

arm64: dts: qcom: sdm845: Add gpi dma node

Message ID 20201130063946.2060317-1-vkoul@kernel.org
State Superseded
Headers show
Series arm64: dts: qcom: sdm845: Add gpi dma node | expand

Commit Message

Vinod Koul Nov. 30, 2020, 6:39 a.m. UTC 
This add the device node for gpi_dma0 and gpi_dma1 instances found in
sdm845.

Signed-off-by: Vinod Koul <vkoul@kernel.org>

---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 45 ++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

-- 
2.26.2

Comments

Bjorn Andersson Dec. 1, 2020, 3:20 a.m. UTC | #1 
On Mon 30 Nov 00:39 CST 2020, Vinod Koul wrote:

> This add the device node for gpi_dma0 and gpi_dma1 instances found in

> sdm845.

> 

> Signed-off-by: Vinod Koul <vkoul@kernel.org>

> ---

>  arch/arm64/boot/dts/qcom/sdm845.dtsi | 45 ++++++++++++++++++++++++++++

>  1 file changed, 45 insertions(+)

> 

> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi

> index 6465a6653ad9..a6f41678794c 100644

> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi

> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi

> @@ -1114,6 +1114,28 @@ opp-128000000 {

>  			};

>  		};

>  

> +		gpi_dma0: dma-controller@800000 {

> +			#dma-cells = <3>;


I know you like dma, but may I have the compatible etc first in the
nodes? Perhaps move #dma-cells down by the other dma- properties?

> +			compatible = "qcom,sdm845-gpi-dma";

> +			reg = <0 0x00800000 0 0x60000>;

> +			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;

> +			dma-channels = <13>;

> +			dma-channel-mask = <0xfa>;

> +			iommus = <&apps_smmu 0x0016 0x0>;

> +		};

> +

>  		qupv3_id_0: geniqup@8c0000 {

>  			compatible = "qcom,geni-se-qup";

>  			reg = <0 0x008c0000 0 0x6000>;

> @@ -1454,6 +1476,29 @@ uart7: serial@89c000 {

>  			};

>  		};

>  

> +		gpi_dma1: dma-controller@0xa00000 {

> +			#dma-cells = <3>;

> +			compatible = "qcom,sdm845-gpi-dma";

> +			reg = <0 0x00a00000 0 0x60000>;

> +			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,

> +				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;

> +			dma-channels = <13>;

> +			dma-channel-mask = <0xfa>;

> +			iommus = <&apps_smmu 0x06d6 0x0>;

> +			status = "disabled";


I don't think it's nice to keep gpi_dma0 enabled and gpi_dma1 disabled.
Either we do both enabled in sdm845.dtsi or we do both disabled and rely
on the boards to enable what they need.

Regards,
Bjorn

> +		};

> +

>  		qupv3_id_1: geniqup@ac0000 {

>  			compatible = "qcom,geni-se-qup";

>  			reg = <0 0x00ac0000 0 0x6000>;

> -- 

> 2.26.2

>
Vinod Koul Dec. 1, 2020, 4:05 a.m. UTC | #2 
On 30-11-20, 21:20, Bjorn Andersson wrote:
> On Mon 30 Nov 00:39 CST 2020, Vinod Koul wrote:
> 
> > This add the device node for gpi_dma0 and gpi_dma1 instances found in
> > sdm845.
> > 
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> >  arch/arm64/boot/dts/qcom/sdm845.dtsi | 45 ++++++++++++++++++++++++++++
> >  1 file changed, 45 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > index 6465a6653ad9..a6f41678794c 100644
> > --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> > @@ -1114,6 +1114,28 @@ opp-128000000 {
> >  			};
> >  		};
> >  
> > +		gpi_dma0: dma-controller@800000 {
> > +			#dma-cells = <3>;
> 
> I know you like dma, but may I have the compatible etc first in the
> nodes? Perhaps move #dma-cells down by the other dma- properties?

Sure thing

> 
> > +			compatible = "qcom,sdm845-gpi-dma";
> > +			reg = <0 0x00800000 0 0x60000>;
> > +			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
> > +			dma-channels = <13>;
> > +			dma-channel-mask = <0xfa>;
> > +			iommus = <&apps_smmu 0x0016 0x0>;
> > +		};
> > +
> >  		qupv3_id_0: geniqup@8c0000 {
> >  			compatible = "qcom,geni-se-qup";
> >  			reg = <0 0x008c0000 0 0x6000>;
> > @@ -1454,6 +1476,29 @@ uart7: serial@89c000 {
> >  			};
> >  		};
> >  
> > +		gpi_dma1: dma-controller@0xa00000 {
> > +			#dma-cells = <3>;
> > +			compatible = "qcom,sdm845-gpi-dma";
> > +			reg = <0 0x00a00000 0 0x60000>;
> > +			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
> > +			dma-channels = <13>;
> > +			dma-channel-mask = <0xfa>;
> > +			iommus = <&apps_smmu 0x06d6 0x0>;
> > +			status = "disabled";
> 
> I don't think it's nice to keep gpi_dma0 enabled and gpi_dma1 disabled.
> Either we do both enabled in sdm845.dtsi or we do both disabled and rely
> on the boards to enable what they need.

Yeah sure, I think enabling them in a board dtsi makes sense, since this
depends on the firmware support..

I will send v2 with updates

Thanks
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 6465a6653ad9..a6f41678794c 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1114,6 +1114,28 @@  opp-128000000 {
 			};
 		};
 
+		gpi_dma0: dma-controller@800000 {
+			#dma-cells = <3>;
+			compatible = "qcom,sdm845-gpi-dma";
+			reg = <0 0x00800000 0 0x60000>;
+			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+			dma-channels = <13>;
+			dma-channel-mask = <0xfa>;
+			iommus = <&apps_smmu 0x0016 0x0>;
+		};
+
 		qupv3_id_0: geniqup@8c0000 {
 			compatible = "qcom,geni-se-qup";
 			reg = <0 0x008c0000 0 0x6000>;
@@ -1454,6 +1476,29 @@  uart7: serial@89c000 {
 			};
 		};
 
+		gpi_dma1: dma-controller@0xa00000 {
+			#dma-cells = <3>;
+			compatible = "qcom,sdm845-gpi-dma";
+			reg = <0 0x00a00000 0 0x60000>;
+			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+			dma-channels = <13>;
+			dma-channel-mask = <0xfa>;
+			iommus = <&apps_smmu 0x06d6 0x0>;
+			status = "disabled";
+		};
+
 		qupv3_id_1: geniqup@ac0000 {
 			compatible = "qcom,geni-se-qup";
 			reg = <0 0x00ac0000 0 0x6000>;