[v5,02/11] ARM: HYP/non-sec: add a barrier after setting SCR.NS==1

Message ID 1405171448-27310-2-git-send-email-ijc@hellion.org.uk
State Accepted
Commit 800c83522ca6a7d6fd0b058f423501b4cc52d6d6
Headers show

Commit Message

Ian Campbell July 12, 2014, 1:23 p.m.
From: Marc Zyngier <marc.zyngier@arm.com>

A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
 arch/arm/cpu/armv7/nonsec_virt.S | 1 +
 1 file changed, 1 insertion(+)


diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 6367e09..12de5c2 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -46,6 +46,7 @@  _secure_monitor:
 	mcr	p15, 0, r1, c1, c1, 0		@ write SCR (with NS bit set)
+	isb
 	mrceq	p15, 0, r0, c12, c0, 1		@ get MVBAR value