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[50.57.142.19]) by mx.google.com with ESMTPS id e1si25165928qag.55.2014.07.16.02.06.39 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 16 Jul 2014 02:06:39 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1X7L8n-0000Q3-Rt; Wed, 16 Jul 2014 09:04:45 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1X7L8m-0000Po-3A for xen-devel@lists.xen.org; Wed, 16 Jul 2014 09:04:44 +0000 Received: from [85.158.143.35:46715] by server-3.bemta-4.messagelabs.com id D0/4D-09960-B2046C35; Wed, 16 Jul 2014 09:04:43 +0000 X-Env-Sender: anup.patel@linaro.org X-Msg-Ref: server-15.tower-21.messagelabs.com!1405501481!18023440!1 X-Originating-IP: [209.85.192.179] X-SpamReason: No, hits=0.0 required=7.0 tests=ML_RADAR_SPEW_LINKS_32, spamassassin: X-StarScan-Received: X-StarScan-Version: 6.11.3; banners=-,-,- X-VirusChecked: Checked Received: (qmail 17852 invoked from network); 16 Jul 2014 09:04:42 -0000 Received: from mail-pd0-f179.google.com (HELO mail-pd0-f179.google.com) (209.85.192.179) by server-15.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 16 Jul 2014 09:04:42 -0000 Received: by mail-pd0-f179.google.com with SMTP id ft15so903128pdb.10 for ; Wed, 16 Jul 2014 02:04:40 -0700 (PDT) X-Received: by 10.66.174.199 with SMTP id bu7mr28624949pac.54.1405501480628; Wed, 16 Jul 2014 02:04:40 -0700 (PDT) Received: from pnqlab006.amcc.com ([182.73.239.130]) by mx.google.com with ESMTPSA id io8sm16332764pbc.96.2014.07.16.02.04.36 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 16 Jul 2014 02:04:39 -0700 (PDT) From: Anup Patel To: xen-devel@lists.xen.org Date: Wed, 16 Jul 2014 14:34:18 +0530 Message-Id: <1405501458-2822-1-git-send-email-anup.patel@linaro.org> X-Mailer: git-send-email 1.7.9.5 Cc: Ian.Campbell@citrix.com, Anup Patel , stefano.stabellini@eu.citrix.com, patches@apm.com, stefano.stabellini@citrix.com, Pranavkumar Sawargaonkar Subject: [Xen-devel] [PATCH] xen/arm: Trap and yield on WFE instructions X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: anup.patel@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: If we have a Guest/DomU with two or more of its VCPUs running on same host CPU then it can quite likely happen that these VCPUs fight for same spinlock and one of them will waste CPU cycles in WFE instruction. This patch makes WFE instruction trap for VCPU and forces VCPU to yield its timeslice. The KVM ARM/ARM64 also does similar thing for handling WFE instructions. (Please refer, https://lists.cs.columbia.edu/pipermail/kvmarm/2013-November/006259.html) In general, this patch is more of an optimization for an oversubscribed system having number of VCPUs more than underlying host CPUs. Signed-off-by: Anup Patel Signed-off-by: Pranavkumar Sawargaonkar Tested-by: Pranavkumar Sawargaonkar --- xen/arch/arm/traps.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 686d8b7..bc9f67a 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -90,7 +90,7 @@ void __cpuinit init_traps(void) /* Setup hypervisor traps */ WRITE_SYSREG(HCR_PTW|HCR_BSU_INNER|HCR_AMO|HCR_IMO|HCR_FMO|HCR_VM| - HCR_TWI|HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP, HCR_EL2); + HCR_TWE|HCR_TWI|HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP, HCR_EL2); isb(); } @@ -1803,16 +1803,21 @@ asmlinkage void do_trap_hypervisor(struct cpu_user_regs *regs) advance_pc(regs, hsr); return; } - /* at the moment we only trap WFI */ - vcpu_block(); - /* The ARM spec declares that even if local irqs are masked in - * the CPSR register, an irq should wake up a cpu from WFI anyway. - * For this reason we need to check for irqs that need delivery, - * ignoring the CPSR register, *after* calling SCHEDOP_block to - * avoid races with vgic_vcpu_inject_irq. - */ - if ( local_events_need_delivery_nomask() ) - vcpu_unblock(current); + if ( hsr.bits & 0x1 ) { + /* Yield the VCPU for WFE */ + vcpu_force_reschedule(current); + } else { + /* Block the VCPU for WFI */ + vcpu_block(); + /* The ARM spec declares that even if local irqs are masked in + * the CPSR register, an irq should wake up a cpu from WFI anyway. + * For this reason we need to check for irqs that need delivery, + * ignoring the CPSR register, *after* calling SCHEDOP_block to + * avoid races with vgic_vcpu_inject_irq. + */ + if ( local_events_need_delivery_nomask() ) + vcpu_unblock(current); + } advance_pc(regs, hsr); break; case HSR_EC_CP15_32: