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[Xen-devel,v2] xen/arm: Trap and yield on WFE instructions

Message ID 1405506735-19025-1-git-send-email-anup.patel@linaro.org
State New
Headers show

Commit Message

Anup Patel July 16, 2014, 10:32 a.m. UTC 
If we have a Guest/DomU with two or more of its VCPUs running
on same host CPU then it can quite likely happen that these
VCPUs fight for same spinlock and one of them will waste CPU
cycles in WFE instruction. This patch makes WFE instruction
trap for VCPU and forces VCPU to yield its timeslice.

The KVM ARM/ARM64 also does similar thing for handling WFE
instructions. (Please refer,
https://lists.cs.columbia.edu/pipermail/kvmarm/2013-November/006259.html)

In general, this patch is more of an optimization for an
oversubscribed system having number of VCPUs more than
underlying host CPUs.

Changes since V1:
 - Added separate member in union hsr for decoding WFI/WFE
   related info.

Signed-off-by: Anup Patel <anup.patel@linaro.org>
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
Tested-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
---
 xen/arch/arm/traps.c            |   27 ++++++++++++++++-----------
 xen/include/asm-arm/processor.h |    9 +++++++++
 2 files changed, 25 insertions(+), 11 deletions(-)
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Patch

diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 686d8b7..632b8ea 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -90,7 +90,7 @@  void __cpuinit init_traps(void)
 
     /* Setup hypervisor traps */
     WRITE_SYSREG(HCR_PTW|HCR_BSU_INNER|HCR_AMO|HCR_IMO|HCR_FMO|HCR_VM|
-                 HCR_TWI|HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP, HCR_EL2);
+                 HCR_TWE|HCR_TWI|HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP, HCR_EL2);
     isb();
 }
 
@@ -1803,16 +1803,21 @@  asmlinkage void do_trap_hypervisor(struct cpu_user_regs *regs)
             advance_pc(regs, hsr);
             return;
         }
-        /* at the moment we only trap WFI */
-        vcpu_block();
-        /* The ARM spec declares that even if local irqs are masked in
-         * the CPSR register, an irq should wake up a cpu from WFI anyway.
-         * For this reason we need to check for irqs that need delivery,
-         * ignoring the CPSR register, *after* calling SCHEDOP_block to
-         * avoid races with vgic_vcpu_inject_irq.
-         */
-        if ( local_events_need_delivery_nomask() )
-            vcpu_unblock(current);
+        if ( hsr.wfi_wfe.ti ) {
+            /* Yield the VCPU for WFE */
+            vcpu_force_reschedule(current);
+        } else {
+            /* Block the VCPU for WFI */
+            vcpu_block();
+            /* The ARM spec declares that even if local irqs are masked in
+             * the CPSR register, an irq should wake up a cpu from WFI anyway.
+             * For this reason we need to check for irqs that need delivery,
+             * ignoring the CPSR register, *after* calling SCHEDOP_block to
+             * avoid races with vgic_vcpu_inject_irq.
+             */
+            if ( local_events_need_delivery_nomask() )
+                vcpu_unblock(current);
+        }
         advance_pc(regs, hsr);
         break;
     case HSR_EC_CP15_32:
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index bdfff4e..cd1db4d 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -276,6 +276,15 @@  union hsr {
         unsigned long ec:6;    /* Exception Class */
     } cond;
 
+    struct hsr_wfi_wfe {
+	unsigned long ti:1;    /* Trapped instruction */
+        unsigned long sbzp:19;
+        unsigned long cc:4;    /* Condition Code */
+        unsigned long ccvalid:1;/* CC Valid */
+        unsigned long len:1;   /* Instruction length */
+        unsigned long ec:6;    /* Exception Class */
+    } wfi_wfe;
+
     /* reg, reg0, reg1 are 4 bits on AArch32, the fifth bit is sbzp. */
     struct hsr_cp32 {
         unsigned long read:1;  /* Direction */