| Message ID | 1406217175-30267-4-git-send-email-alex.bennee@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
On 24 July 2014 16:52, Alex Bennée <alex.bennee@linaro.org> wrote: > The aarch64 architecture only support 4k+ pages so using a smaller value > for QEMU's internal page table handling only makes us less efficient. > > Signed-off-by: Alex Bennée <alex.bennee@linaro.org> > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index c83f249..33359b9 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -1051,11 +1051,18 @@ bool write_cpustate_to_list(ARMCPU *cpu); > #if defined(CONFIG_USER_ONLY) > #define TARGET_PAGE_BITS 12 > #else > -/* The ARM MMU allows 1k pages. */ > -/* ??? Linux doesn't actually use these, and they're deprecated in recent > - architecture revisions. Maybe a configure option to disable them. */ > +#if defined(TARGET_AARCH64) > +/* You can't configure 1k pages on aarch64 hardware */ "AArch64" (here and in commit messages). Also, qemu-system-aarch64 still supports all the 32 bit CPUs, including the ARMv5 ones (v5 is the last revision that supported 1K pages). So we'd have to at least remove those CPUs from the TARGET_AARCH64 system emulator compilation, if we can't come up with anything cleverer. thanks -- PMM
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index c83f249..33359b9 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1051,11 +1051,18 @@ bool write_cpustate_to_list(ARMCPU *cpu); #if defined(CONFIG_USER_ONLY) #define TARGET_PAGE_BITS 12 #else -/* The ARM MMU allows 1k pages. */ -/* ??? Linux doesn't actually use these, and they're deprecated in recent - architecture revisions. Maybe a configure option to disable them. */ +#if defined(TARGET_AARCH64) +/* You can't configure 1k pages on aarch64 hardware */ +#define TARGET_PAGE_BITS 12 +#else +/* The ARM MMU allows 1k pages - although they are not used by Linux + * FIXME?: they're deprecated in recent architecture revisions and + * this does create a performance hit. Maybe a configure option to + * disable them? + */ #define TARGET_PAGE_BITS 10 #endif +#endif #if defined(TARGET_AARCH64) # define TARGET_PHYS_ADDR_SPACE_BITS 48
The aarch64 architecture only support 4k+ pages so using a smaller value for QEMU's internal page table handling only makes us less efficient. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>