diff mbox series

[v10,06/23] riscv: Fix Canaan Kendryte K210 device tree

Message ID 20201213135056.24446-7-damien.lemoal@wdc.com
State Accepted
Commit 93c2ce1ee77e2db5d99f00bb7f79c34ab8439f17
Headers show
Series RISC-V Kendryte K210 support improvements | expand

Commit Message

Damien Le Moal Dec. 13, 2020, 1:50 p.m. UTC
Remove the clocks property from the cpu and clint nodes as these are
ignored. Also remove the clock-frequency property from the cpu nodes as
riscv relies on the timebase-frequency property.

Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
---
 arch/riscv/boot/dts/canaan/k210.dtsi | 5 -----
 1 file changed, 5 deletions(-)

Comments

Anup Patel Dec. 28, 2020, 12:03 p.m. UTC | #1
On Sun, Dec 13, 2020 at 7:21 PM Damien Le Moal <damien.lemoal@wdc.com> wrote:
>

> Remove the clocks property from the cpu and clint nodes as these are

> ignored. Also remove the clock-frequency property from the cpu nodes as

> riscv relies on the timebase-frequency property.

>

> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>

> ---

>  arch/riscv/boot/dts/canaan/k210.dtsi | 5 -----

>  1 file changed, 5 deletions(-)

>

> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi

> index d2d0ff645632..354b263195a3 100644

> --- a/arch/riscv/boot/dts/canaan/k210.dtsi

> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi

> @@ -38,8 +38,6 @@ cpu0: cpu@0 {

>                         i-cache-block-size = <64>;

>                         d-cache-size = <0x8000>;

>                         d-cache-block-size = <64>;

> -                       clocks = <&sysctl K210_CLK_CPU>;

> -                       clock-frequency = <390000000>;

>                         cpu0_intc: interrupt-controller {

>                                 #interrupt-cells = <1>;

>                                 interrupt-controller;

> @@ -56,8 +54,6 @@ cpu1: cpu@1 {

>                         i-cache-block-size = <64>;

>                         d-cache-size = <0x8000>;

>                         d-cache-block-size = <64>;

> -                       clocks = <&sysctl K210_CLK_CPU>;

> -                       clock-frequency = <390000000>;

>                         cpu1_intc: interrupt-controller {

>                                 #interrupt-cells = <1>;

>                                 interrupt-controller;

> @@ -101,7 +97,6 @@ clint0: clint@2000000 {

>                         reg = <0x2000000 0xC000>;

>                         interrupts-extended =  <&cpu0_intc 3 &cpu0_intc 7

>                                                 &cpu1_intc 3 &cpu1_intc 7>;

> -                       clocks = <&sysctl K210_CLK_ACLK>;

>                 };

>

>                 plic0: interrupt-controller@c000000 {

> --

> 2.29.2

>

>

> _______________________________________________

> linux-riscv mailing list

> linux-riscv@lists.infradead.org

> http://lists.infradead.org/mailman/listinfo/linux-riscv


Looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>


Regards,
Anup
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index d2d0ff645632..354b263195a3 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -38,8 +38,6 @@  cpu0: cpu@0 {
 			i-cache-block-size = <64>;
 			d-cache-size = <0x8000>;
 			d-cache-block-size = <64>;
-			clocks = <&sysctl K210_CLK_CPU>;
-			clock-frequency = <390000000>;
 			cpu0_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				interrupt-controller;
@@ -56,8 +54,6 @@  cpu1: cpu@1 {
 			i-cache-block-size = <64>;
 			d-cache-size = <0x8000>;
 			d-cache-block-size = <64>;
-			clocks = <&sysctl K210_CLK_CPU>;
-			clock-frequency = <390000000>;
 			cpu1_intc: interrupt-controller {
 				#interrupt-cells = <1>;
 				interrupt-controller;
@@ -101,7 +97,6 @@  clint0: clint@2000000 {
 			reg = <0x2000000 0xC000>;
 			interrupts-extended =  <&cpu0_intc 3 &cpu0_intc 7
 						&cpu1_intc 3 &cpu1_intc 7>;
-			clocks = <&sysctl K210_CLK_ACLK>;
 		};
 
 		plic0: interrupt-controller@c000000 {