[v8,3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property

Message ID 1406611711-25112-4-git-send-email-thomas.ab@samsung.com
State New
Headers show

Commit Message

Thomas Abraham July 29, 2014, 5:28 a.m.
For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific cpufreq driver
to using generic cpufreq drivers.

Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
 arch/arm/boot/dts/exynos4210-origen.dts         |    6 ++++
 arch/arm/boot/dts/exynos4210-trats.dts          |    6 ++++
 arch/arm/boot/dts/exynos4210-universal_c210.dts |    6 ++++
 arch/arm/boot/dts/exynos4210.dtsi               |   12 +++++++
 arch/arm/boot/dts/exynos5250-arndale.dts        |    6 ++++
 arch/arm/boot/dts/exynos5250-cros-common.dtsi   |    6 ++++
 arch/arm/boot/dts/exynos5250-smdk5250.dts       |    6 ++++
 arch/arm/boot/dts/exynos5250.dtsi               |   23 ++++++++++++++
 arch/arm/boot/dts/exynos5420-smdk5420.dts       |    6 ++++
 arch/arm/boot/dts/exynos5420.dtsi               |   38 +++++++++++++++++++++++
 10 files changed, 115 insertions(+)

Comments

Tomasz Figa July 29, 2014, 10:31 a.m. | #1
Hi Thomas,

Other than the same question about 400 MHz OPP for Exynos4210, I have
also few more inline.

On 29.07.2014 07:28, Thomas Abraham wrote:
> For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU
> regulator supply properties for migrating from Exynos specific cpufreq driver
> to using generic cpufreq drivers.
> 
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> ---
>  arch/arm/boot/dts/exynos4210-origen.dts         |    6 ++++
>  arch/arm/boot/dts/exynos4210-trats.dts          |    6 ++++
>  arch/arm/boot/dts/exynos4210-universal_c210.dts |    6 ++++
>  arch/arm/boot/dts/exynos4210.dtsi               |   12 +++++++
>  arch/arm/boot/dts/exynos5250-arndale.dts        |    6 ++++
>  arch/arm/boot/dts/exynos5250-cros-common.dtsi   |    6 ++++
>  arch/arm/boot/dts/exynos5250-smdk5250.dts       |    6 ++++
>  arch/arm/boot/dts/exynos5250.dtsi               |   23 ++++++++++++++
>  arch/arm/boot/dts/exynos5420-smdk5420.dts       |    6 ++++

There are more Exynos5420-based boards supported in mainline. If you do
not have necessary data and/or hardware to fully enable the new driver
on them, you should add responsible people on Cc list, so at least they
know they have one more item on their TODO list. Added them for you.

>  arch/arm/boot/dts/exynos5420.dtsi               |   38 +++++++++++++++++++++++
>  10 files changed, 115 insertions(+)

[snip]

> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index 492e1ef..876247a 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -63,6 +63,29 @@
>  			compatible = "arm,cortex-a15";
>  			reg = <0>;
>  			clock-frequency = <1700000000>;
> +
> +			clocks = <&clock CLK_ARM_CLK>;
> +			clock-names = "cpu";
> +			clock-latency = <200000>;

Where does this latency value comes from? How did you calculate it?

For example, on Exynos4210, for all operating points added by your
patches, the highest PLL locking latency will be 60uS, because the
highest PDIV value would be 6 and PLL lock time is PDIV*240 ticks of 24
MHz reference clock.

> +
> +			operating-points = <
> +				1700000 1300000
> +				1600000 1250000

[snip]

> diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> index 6052aa9..084e587 100644
> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
> @@ -24,6 +24,12 @@
>  		bootargs = "console=ttySAC2,115200 init=/linuxrc";
>  	};
>  
> +	cpus {

Is there no regulator for cpu0?

> +		cpu@4 {
> +			cpu0-supply = <&buck6_reg>;
> +		};
> +	};
> +
>  	fixed-rate-clocks {
>  		oscclk {
>  			compatible = "samsung,exynos5420-oscclk";
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
> index cb2b70e..1116d55 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi

[snip]

>  
>  		cpu1: cpu@1 {
> @@ -69,6 +87,7 @@
>  			reg = <0x1>;
>  			clock-frequency = <1800000000>;
>  			cci-control-port = <&cci_control1>;
> +			clock-latency = <200000>;

Do you need to specify this property for every CPU or rather just for
those which have operating points specified?

Best regards,
Tomasz
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Thomas Abraham July 29, 2014, noon | #2
Hi Tomasz,

On Tue, Jul 29, 2014 at 4:01 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> Hi Thomas,
>
> Other than the same question about 400 MHz OPP for Exynos4210, I have
> also few more inline.
>
> On 29.07.2014 07:28, Thomas Abraham wrote:
>> For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU
>> regulator supply properties for migrating from Exynos specific cpufreq driver
>> to using generic cpufreq drivers.
>>
>> Cc: Kukjin Kim <kgene.kim@samsung.com>
>> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
>> ---
>>  arch/arm/boot/dts/exynos4210-origen.dts         |    6 ++++
>>  arch/arm/boot/dts/exynos4210-trats.dts          |    6 ++++
>>  arch/arm/boot/dts/exynos4210-universal_c210.dts |    6 ++++
>>  arch/arm/boot/dts/exynos4210.dtsi               |   12 +++++++
>>  arch/arm/boot/dts/exynos5250-arndale.dts        |    6 ++++
>>  arch/arm/boot/dts/exynos5250-cros-common.dtsi   |    6 ++++
>>  arch/arm/boot/dts/exynos5250-smdk5250.dts       |    6 ++++
>>  arch/arm/boot/dts/exynos5250.dtsi               |   23 ++++++++++++++
>>  arch/arm/boot/dts/exynos5420-smdk5420.dts       |    6 ++++
>
> There are more Exynos5420-based boards supported in mainline. If you do
> not have necessary data and/or hardware to fully enable the new driver
> on them, you should add responsible people on Cc list, so at least they
> know they have one more item on their TODO list. Added them for you.

Thanks!. Will do that next time.

>
>>  arch/arm/boot/dts/exynos5420.dtsi               |   38 +++++++++++++++++++++++
>>  10 files changed, 115 insertions(+)
>
> [snip]
>
>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
>> index 492e1ef..876247a 100644
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -63,6 +63,29 @@
>>                       compatible = "arm,cortex-a15";
>>                       reg = <0>;
>>                       clock-frequency = <1700000000>;
>> +
>> +                     clocks = <&clock CLK_ARM_CLK>;
>> +                     clock-names = "cpu";
>> +                     clock-latency = <200000>;
>
> Where does this latency value comes from? How did you calculate it?
>
> For example, on Exynos4210, for all operating points added by your
> patches, the highest PLL locking latency will be 60uS, because the
> highest PDIV value would be 6 and PLL lock time is PDIV*240 ticks of 24
> MHz reference clock.

Since the CPU clock is a composite clock with dividers and muxes, the
latency includes the settling time for these clock blocks as well. I
have not made any measurements of the clock transition latency.

>
>> +
>> +                     operating-points = <
>> +                             1700000 1300000
>> +                             1600000 1250000
>
> [snip]
>
>> diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> index 6052aa9..084e587 100644
>> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>> @@ -24,6 +24,12 @@
>>               bootargs = "console=ttySAC2,115200 init=/linuxrc";
>>       };
>>
>> +     cpus {
>
> Is there no regulator for cpu0?

This was a mistake. I did not intend to add regulator for cpu4 as well
but somehow I missed it. I will remove it in the next version.

>
>> +             cpu@4 {
>> +                     cpu0-supply = <&buck6_reg>;
>> +             };
>> +     };
>> +
>>       fixed-rate-clocks {
>>               oscclk {
>>                       compatible = "samsung,exynos5420-oscclk";
>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
>> index cb2b70e..1116d55 100644
>> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>
> [snip]
>
>>
>>               cpu1: cpu@1 {
>> @@ -69,6 +87,7 @@
>>                       reg = <0x1>;
>>                       clock-frequency = <1800000000>;
>>                       cci-control-port = <&cci_control1>;
>> +                     clock-latency = <200000>;
>
> Do you need to specify this property for every CPU or rather just for
> those which have operating points specified?

The big.little cpufreq driver expects each CPU to have the clock
latency specified.

Thanks,
Thomas.

>
> Best regards,
> Tomasz
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Andreas Färber July 29, 2014, 12:08 p.m. | #3
Hi Thomas,

Am 29.07.2014 07:28, schrieb Thomas Abraham:
> diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
> index 89ac90f..34bb31c 100644
> --- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
> +++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
> @@ -19,6 +19,12 @@
>  	chosen {
>  	};
>  
> +	cpus {
> +		cpu@0 {
> +			cpu0-supply = <&buck2_reg>;
> +		};
> +	};
> +
>  	pinctrl@11400000 {
>  		/*
>  		 * Disabled pullups since external part has its own pullups and

I've been instructed to dismantle this .dtsi file, so please place this
into exynos5250-snow.dts. It's probably wrong here anyway, since Spring
doesn't use the max77686 but an s5m6787 PMIC.

How do I find out which -supply to specify here for Spring?

Also, wouldn't it make sense to assign a cpu0 label in exynos????.dtsi
to override it via &cpu0 { ... };?

Regards,
Andreas
Tomasz Figa July 29, 2014, 12:10 p.m. | #4
On 29.07.2014 14:00, Thomas Abraham wrote:

[snip]

>>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
>>> index 492e1ef..876247a 100644
>>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>>> @@ -63,6 +63,29 @@
>>>                       compatible = "arm,cortex-a15";
>>>                       reg = <0>;
>>>                       clock-frequency = <1700000000>;
>>> +
>>> +                     clocks = <&clock CLK_ARM_CLK>;
>>> +                     clock-names = "cpu";
>>> +                     clock-latency = <200000>;
>>
>> Where does this latency value comes from? How did you calculate it?
>>
>> For example, on Exynos4210, for all operating points added by your
>> patches, the highest PLL locking latency will be 60uS, because the
>> highest PDIV value would be 6 and PLL lock time is PDIV*240 ticks of 24
>> MHz reference clock.
> 
> Since the CPU clock is a composite clock with dividers and muxes, the
> latency includes the settling time for these clock blocks as well. I
> have not made any measurements of the clock transition latency.
> 

It might be more reasonable to find out correct latency values instead
of specifying a rather random number.

>>
>>> +
>>> +                     operating-points = <
>>> +                             1700000 1300000
>>> +                             1600000 1250000
>>
>> [snip]
>>
>>> diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>>> index 6052aa9..084e587 100644
>>> --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
>>> +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
>>> @@ -24,6 +24,12 @@
>>>               bootargs = "console=ttySAC2,115200 init=/linuxrc";
>>>       };
>>>
>>> +     cpus {
>>
>> Is there no regulator for cpu0?
> 
> This was a mistake. I did not intend to add regulator for cpu4 as well
> but somehow I missed it. I will remove it in the next version.
> 
>>>
>>>               cpu1: cpu@1 {
>>> @@ -69,6 +87,7 @@
>>>                       reg = <0x1>;
>>>                       clock-frequency = <1800000000>;
>>>                       cci-control-port = <&cci_control1>;
>>> +                     clock-latency = <200000>;
>>
>> Do you need to specify this property for every CPU or rather just for
>> those which have operating points specified?
> 
> The big.little cpufreq driver expects each CPU to have the clock
> latency specified.

OK, apparently this is the case, even though it seems a bit
unreasonable, as they all share the same clock.

Best regards,
Tomasz
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Thomas Abraham July 29, 2014, 12:35 p.m. | #5
Hi Andreas,

On Tue, Jul 29, 2014 at 5:38 PM, Andreas Färber <afaerber@suse.de> wrote:
> Hi Thomas,
>
> Am 29.07.2014 07:28, schrieb Thomas Abraham:
>> diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
>> index 89ac90f..34bb31c 100644
>> --- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
>> @@ -19,6 +19,12 @@
>>       chosen {
>>       };
>>
>> +     cpus {
>> +             cpu@0 {
>> +                     cpu0-supply = <&buck2_reg>;
>> +             };
>> +     };
>> +
>>       pinctrl@11400000 {
>>               /*
>>                * Disabled pullups since external part has its own pullups and
>
> I've been instructed to dismantle this .dtsi file, so please place this
> into exynos5250-snow.dts. It's probably wrong here anyway, since Spring
> doesn't use the max77686 but an s5m6787 PMIC.

Ok, I will move this to exynos5250-snow.dts.

>
> How do I find out which -supply to specify here for Spring?

This information can be found in the Spring board schematic.

>
> Also, wouldn't it make sense to assign a cpu0 label in exynos????.dtsi
> to override it via &cpu0 { ... };?

Sorry, I did not understand the question.

Thanks,
Thomas.

>
> Regards,
> Andreas
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Andreas Färber July 29, 2014, 12:42 p.m. | #6
Hi Thomas,

Am 29.07.2014 14:35, schrieb Thomas Abraham:
> On Tue, Jul 29, 2014 at 5:38 PM, Andreas Färber <afaerber@suse.de> wrote:
>> Am 29.07.2014 07:28, schrieb Thomas Abraham:
>>> diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
>>> index 89ac90f..34bb31c 100644
>>> --- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
>>> +++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
>>> @@ -19,6 +19,12 @@
>>>       chosen {
>>>       };
>>>
>>> +     cpus {
>>> +             cpu@0 {
>>> +                     cpu0-supply = <&buck2_reg>;
>>> +             };
>>> +     };
>>> +
>>>       pinctrl@11400000 {
>>>               /*
>>>                * Disabled pullups since external part has its own pullups and
>>
>> I've been instructed to dismantle this .dtsi file, so please place this
>> into exynos5250-snow.dts. It's probably wrong here anyway, since Spring
>> doesn't use the max77686 but an s5m6787 PMIC.
> 
> Ok, I will move this to exynos5250-snow.dts.
> 
>>
>> How do I find out which -supply to specify here for Spring?
> 
> This information can be found in the Spring board schematic.

Are those available publicly somewhere? I guess not...

>> Also, wouldn't it make sense to assign a cpu0 label in exynos????.dtsi
>> to override it via &cpu0 { ... };?
> 
> Sorry, I did not understand the question.

Instead of adding

cpus { cpu@0 { ... }; };

to the board's / node, I am suggesting you do in the SoC's .dtsi:

- cpu@0 {
+ cpu0: cpu@0 {

and then in the board's file after / { ... }; add the following:

&cpu0 {
	cpu0-supply = <&buck2_reg>;
};

This is the new preferred way to override or extend inherited nodes, I
am told. (&cpu0 should be inserted in alphabetical order then.)

Cheers,
Andreas
Thomas Abraham July 29, 2014, 12:51 p.m. | #7
Hi Andreas,

On Tue, Jul 29, 2014 at 6:12 PM, Andreas Färber <afaerber@suse.de> wrote:
> Hi Thomas,
>
> Am 29.07.2014 14:35, schrieb Thomas Abraham:
>> On Tue, Jul 29, 2014 at 5:38 PM, Andreas Färber <afaerber@suse.de> wrote:
>>> Am 29.07.2014 07:28, schrieb Thomas Abraham:
>>>> diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
>>>> index 89ac90f..34bb31c 100644
>>>> --- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
>>>> +++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
>>>> @@ -19,6 +19,12 @@
>>>>       chosen {
>>>>       };
>>>>
>>>> +     cpus {
>>>> +             cpu@0 {
>>>> +                     cpu0-supply = <&buck2_reg>;
>>>> +             };
>>>> +     };
>>>> +
>>>>       pinctrl@11400000 {
>>>>               /*
>>>>                * Disabled pullups since external part has its own pullups and
>>>
>>> I've been instructed to dismantle this .dtsi file, so please place this
>>> into exynos5250-snow.dts. It's probably wrong here anyway, since Spring
>>> doesn't use the max77686 but an s5m6787 PMIC.
>>
>> Ok, I will move this to exynos5250-snow.dts.
>>
>>>
>>> How do I find out which -supply to specify here for Spring?
>>
>> This information can be found in the Spring board schematic.
>
> Are those available publicly somewhere? I guess not...

I am not sure if it is available publicly. Doug (Cc'ed on this email)
might have it.

>
>>> Also, wouldn't it make sense to assign a cpu0 label in exynos????.dtsi
>>> to override it via &cpu0 { ... };?
>>
>> Sorry, I did not understand the question.
>
> Instead of adding
>
> cpus { cpu@0 { ... }; };
>
> to the board's / node, I am suggesting you do in the SoC's .dtsi:
>
> - cpu@0 {
> + cpu0: cpu@0 {
>
> and then in the board's file after / { ... }; add the following:
>
> &cpu0 {
>         cpu0-supply = <&buck2_reg>;
> };
>
> This is the new preferred way to override or extend inherited nodes, I
> am told. (&cpu0 should be inserted in alphabetical order then.)

Okay, thanks for the clarification. I will update as per the preferred way.

Thanks,
Thomas.

>
> Cheers,
> Andreas
>
> --
> SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
--
To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Patch

diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index f767c42..49a97fc 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -33,6 +33,12 @@ 
 		bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
 	};
 
+	cpus {
+		cpu@0 {
+			cpu0-supply = <&buck1_reg>;
+		};
+	};
+
 	regulators {
 		compatible = "simple-bus";
 		#address-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index f516da9..fe32b6a 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -30,6 +30,12 @@ 
 		bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
 	};
 
+	cpus {
+		cpu: cpu@0 {
+			cpu0-supply = <&varm_breg>;
+		};
+	};
+
 	regulators {
 		compatible = "simple-bus";
 
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d50eb3a..8ab12d6 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -28,6 +28,12 @@ 
 		bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1";
 	};
 
+	cpus {
+		cpu: cpu@0 {
+			cpu0-supply = <&vdd_arm_reg>;
+		};
+	};
+
 	sysram@02020000 {
 		smp-sysram@0 {
 			status = "disabled";
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index bcc9e63..cd68030 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -39,6 +39,18 @@ 
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0x900>;
+			clocks = <&clock CLK_ARM_CLK>;
+			clock-names = "cpu";
+			clock-latency = <200000>;
+
+			operating-points = <
+				1200000 1250000
+				1000000 1150000
+				800000	1075000
+				500000	975000
+				400000	975000
+				200000	950000
+			>;
 		};
 
 		cpu@901 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..d9b803b 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -26,6 +26,12 @@ 
 		bootargs = "console=ttySAC2,115200";
 	};
 
+	cpus {
+		cpu@0 {
+			cpu0-supply = <&buck2_reg>;
+		};
+	};
+
 	rtc@101E0000 {
 		status = "okay";
 	};
diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
index 89ac90f..34bb31c 100644
--- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
@@ -19,6 +19,12 @@ 
 	chosen {
 	};
 
+	cpus {
+		cpu@0 {
+			cpu0-supply = <&buck2_reg>;
+		};
+	};
+
 	pinctrl@11400000 {
 		/*
 		 * Disabled pullups since external part has its own pullups and
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index b4b35ad..cf38808 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -27,6 +27,12 @@ 
 		bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
 	};
 
+	cpus {
+		cpu@0 {
+			cpu0-supply = <&buck2_reg>;
+		};
+	};
+
 	rtc@101E0000 {
 		status = "okay";
 	};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 492e1ef..876247a 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -63,6 +63,29 @@ 
 			compatible = "arm,cortex-a15";
 			reg = <0>;
 			clock-frequency = <1700000000>;
+
+			clocks = <&clock CLK_ARM_CLK>;
+			clock-names = "cpu";
+			clock-latency = <200000>;
+
+			operating-points = <
+				1700000 1300000
+				1600000 1250000
+				1500000 1225000
+				1400000 1200000
+				1300000 1150000
+				1200000 1125000
+				1100000 1100000
+				1000000 1075000
+				 900000 1050000
+				 800000 1025000
+				 700000 1012500
+				 600000 1000000
+				 500000  975000
+				 400000  950000
+				 300000  937500
+				 200000  925000
+			>;
 		};
 		cpu@1 {
 			device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 6052aa9..084e587 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -24,6 +24,12 @@ 
 		bootargs = "console=ttySAC2,115200 init=/linuxrc";
 	};
 
+	cpus {
+		cpu@4 {
+			cpu0-supply = <&buck6_reg>;
+		};
+	};
+
 	fixed-rate-clocks {
 		oscclk {
 			compatible = "samsung,exynos5420-oscclk";
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index cb2b70e..1116d55 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -59,8 +59,26 @@ 
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0x0>;
+			clocks = <&clock CLK_ARM_CLK>;
+			clock-names = "cpu-cluster.0";
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			clock-latency = <200000>;
+
+			operating-points = <
+				1800000 1250000
+				1700000 1212500
+				1600000 1175000
+				1500000 1137500
+				1400000 1112500
+				1300000 1062500
+				1200000 1037500
+				1100000 1012500
+				1000000 987500
+				 900000 962500
+				 800000 937500
+				 700000 912500
+			>;
 		};
 
 		cpu1: cpu@1 {
@@ -69,6 +87,7 @@ 
 			reg = <0x1>;
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			clock-latency = <200000>;
 		};
 
 		cpu2: cpu@2 {
@@ -77,6 +96,7 @@ 
 			reg = <0x2>;
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			clock-latency = <200000>;
 		};
 
 		cpu3: cpu@3 {
@@ -85,14 +105,29 @@ 
 			reg = <0x3>;
 			clock-frequency = <1800000000>;
 			cci-control-port = <&cci_control1>;
+			clock-latency = <200000>;
 		};
 
 		cpu4: cpu@100 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x100>;
+			clocks = <&clock CLK_KFC_CLK>;
+			clock-names = "cpu-cluster.1";
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			clock-latency = <200000>;
+
+			operating-points = <
+				1300000 1275000
+				1200000 1212500
+				1100000 1162500
+				1000000 1112500
+				 900000 1062500
+				 800000 1025000
+				 700000 975000
+				 600000 937500
+			>;
 		};
 
 		cpu5: cpu@101 {
@@ -101,6 +136,7 @@ 
 			reg = <0x101>;
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			clock-latency = <200000>;
 		};
 
 		cpu6: cpu@102 {
@@ -109,6 +145,7 @@ 
 			reg = <0x102>;
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			clock-latency = <200000>;
 		};
 
 		cpu7: cpu@103 {
@@ -117,6 +154,7 @@ 
 			reg = <0x103>;
 			clock-frequency = <1000000000>;
 			cci-control-port = <&cci_control0>;
+			clock-latency = <200000>;
 		};
 	};