[v9,6/6] clk: samsung: remove unused clock aliases and update clock flags

Message ID 1406707663-16656-7-git-send-email-thomas.ab@samsung.com
State New
Headers show

Commit Message

Thomas Abraham July 30, 2014, 8:07 a.m.
With some of the Exynos SoCs switched over to use the generic CPUfreq drivers,
the unused clock aliases can be removed. In addition to this, the individual
clock blocks which are now encapsulated with the consolidate CPU clock type
can now be marked with read-only flags.

Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c    |   48 +++++++++++++++++-----------------
 drivers/clk/samsung/clk-exynos5250.c |   19 ++++++++------
 drivers/clk/samsung/clk-exynos5420.c |   27 ++++++++++++-------
 3 files changed, 53 insertions(+), 41 deletions(-)

Comments

Tomasz Figa July 31, 2014, 2:13 p.m. | #1
On 30.07.2014 10:07, Thomas Abraham wrote:
> With some of the Exynos SoCs switched over to use the generic CPUfreq drivers,
> the unused clock aliases can be removed. In addition to this, the individual
> clock blocks which are now encapsulated with the consolidate CPU clock type
> can now be marked with read-only flags.

[snip]

> @@ -1500,6 +1499,7 @@ static void __init exynos4_clk_init(struct device_node *np,
>  		exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
>  		_get_rate("sclk_apll"),	_get_rate("sclk_mpll"),
>  		_get_rate("sclk_epll"), _get_rate("sclk_vpll"),
> +		exynos4_soc == EXYNOS4210 ? _get_rate("armclk") :
>  		_get_rate("div_core2"));

I believe "div_core2" should work fine here for all SoCs without the
need for this if.

>  }
>  
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index e19e365..1d958f1 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c

[snip]

> @@ -848,6 +851,6 @@ static void __init exynos5250_clk_init(struct device_node *np)
>  	samsung_clk_of_add_provider(np, ctx);
>  
>  	pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
> -			_get_rate("div_arm2"));
> +			_get_rate("armclk"));

Similarly here, no need for this change.

Best regards,
Tomasz
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Thomas Abraham July 31, 2014, 6:24 p.m. | #2
Hi Tomasz,

On Thu, Jul 31, 2014 at 7:43 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> On 30.07.2014 10:07, Thomas Abraham wrote:
>> With some of the Exynos SoCs switched over to use the generic CPUfreq drivers,
>> the unused clock aliases can be removed. In addition to this, the individual
>> clock blocks which are now encapsulated with the consolidate CPU clock type
>> can now be marked with read-only flags.
>
> [snip]
>
>> @@ -1500,6 +1499,7 @@ static void __init exynos4_clk_init(struct device_node *np,
>>               exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
>>               _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
>>               _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
>> +             exynos4_soc == EXYNOS4210 ? _get_rate("armclk") :
>>               _get_rate("div_core2"));
>
> I believe "div_core2" should work fine here for all SoCs without the
> need for this if.

The following patch is a pre-requisite for this patch.
http://www.spinics.net/lists/arm-kernel/msg351540.html

The rate can be obtained from div_core2 as well but with the cpu clock
now registered, the rate can be obtained from the cpu clock instance
instead of the div_core2 divider. And when Exynos4412 also add cpu
clock instance, the 'if' above will be removed.

>
>>  }
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
>> index e19e365..1d958f1 100644
>> --- a/drivers/clk/samsung/clk-exynos5250.c
>> +++ b/drivers/clk/samsung/clk-exynos5250.c
>
> [snip]
>
>> @@ -848,6 +851,6 @@ static void __init exynos5250_clk_init(struct device_node *np)
>>       samsung_clk_of_add_provider(np, ctx);
>>
>>       pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
>> -                     _get_rate("div_arm2"));
>> +                     _get_rate("armclk"));
>
> Similarly here, no need for this change.

Same here. Instead of getting the rate from div_core2 divider block,
the cpu clock instance is used to find the rate. I would prefer to use
cpu clock here. Is there any reason to prefer div_core2 over the cpu
clock instance?

Thanks,
Thomas.

>
> Best regards,
> Tomasz
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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Tomasz Figa July 31, 2014, 6:35 p.m. | #3
On 31.07.2014 20:24, Thomas Abraham wrote:
> Hi Tomasz,
> 
> On Thu, Jul 31, 2014 at 7:43 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
>> On 30.07.2014 10:07, Thomas Abraham wrote:
>>> With some of the Exynos SoCs switched over to use the generic CPUfreq drivers,
>>> the unused clock aliases can be removed. In addition to this, the individual
>>> clock blocks which are now encapsulated with the consolidate CPU clock type
>>> can now be marked with read-only flags.
>>
>> [snip]
>>
>>> @@ -1500,6 +1499,7 @@ static void __init exynos4_clk_init(struct device_node *np,
>>>               exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
>>>               _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
>>>               _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
>>> +             exynos4_soc == EXYNOS4210 ? _get_rate("armclk") :
>>>               _get_rate("div_core2"));
>>
>> I believe "div_core2" should work fine here for all SoCs without the
>> need for this if.
> 
> The following patch is a pre-requisite for this patch.
> http://www.spinics.net/lists/arm-kernel/msg351540.html
> 
> The rate can be obtained from div_core2 as well but with the cpu clock
> now registered, the rate can be obtained from the cpu clock instance
> instead of the div_core2 divider. And when Exynos4412 also add cpu
> clock instance, the 'if' above will be removed.
> 
>>
>>>  }
>>>
>>> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
>>> index e19e365..1d958f1 100644
>>> --- a/drivers/clk/samsung/clk-exynos5250.c
>>> +++ b/drivers/clk/samsung/clk-exynos5250.c
>>
>> [snip]
>>
>>> @@ -848,6 +851,6 @@ static void __init exynos5250_clk_init(struct device_node *np)
>>>       samsung_clk_of_add_provider(np, ctx);
>>>
>>>       pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
>>> -                     _get_rate("div_arm2"));
>>> +                     _get_rate("armclk"));
>>
>> Similarly here, no need for this change.
> 
> Same here. Instead of getting the rate from div_core2 divider block,
> the cpu clock instance is used to find the rate. I would prefer to use
> cpu clock here. Is there any reason to prefer div_core2 over the cpu
> clock instance?

Well, the reason is simple: if you don't need to change something (i.e.
the change doesn't have any advantages), don't change it.

There is no difference between obtaining the rate from div_{arm,core}2
and armclk, so I don't see the point of changing this.

In fact now when thinking of it, this has revealed one hole that will be
unhandled by your code - if cpufreq is disabled and the bootloader
configures div_{arm,core}{,2} with non-zero values, armclk will return
incorrect rate. However since I haven't observed such case on existing
platforms, fixing this might be done on top of this series, in a
separate patch.

Best regards,
Tomasz
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Thomas Abraham July 31, 2014, 6:41 p.m. | #4
On Fri, Aug 1, 2014 at 12:05 AM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> On 31.07.2014 20:24, Thomas Abraham wrote:
>> Hi Tomasz,
>>
>> On Thu, Jul 31, 2014 at 7:43 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
>>> On 30.07.2014 10:07, Thomas Abraham wrote:
>>>> With some of the Exynos SoCs switched over to use the generic CPUfreq drivers,
>>>> the unused clock aliases can be removed. In addition to this, the individual
>>>> clock blocks which are now encapsulated with the consolidate CPU clock type
>>>> can now be marked with read-only flags.
>>>
>>> [snip]
>>>
>>>> @@ -1500,6 +1499,7 @@ static void __init exynos4_clk_init(struct device_node *np,
>>>>               exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
>>>>               _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
>>>>               _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
>>>> +             exynos4_soc == EXYNOS4210 ? _get_rate("armclk") :
>>>>               _get_rate("div_core2"));
>>>
>>> I believe "div_core2" should work fine here for all SoCs without the
>>> need for this if.
>>
>> The following patch is a pre-requisite for this patch.
>> http://www.spinics.net/lists/arm-kernel/msg351540.html
>>
>> The rate can be obtained from div_core2 as well but with the cpu clock
>> now registered, the rate can be obtained from the cpu clock instance
>> instead of the div_core2 divider. And when Exynos4412 also add cpu
>> clock instance, the 'if' above will be removed.
>>
>>>
>>>>  }
>>>>
>>>> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
>>>> index e19e365..1d958f1 100644
>>>> --- a/drivers/clk/samsung/clk-exynos5250.c
>>>> +++ b/drivers/clk/samsung/clk-exynos5250.c
>>>
>>> [snip]
>>>
>>>> @@ -848,6 +851,6 @@ static void __init exynos5250_clk_init(struct device_node *np)
>>>>       samsung_clk_of_add_provider(np, ctx);
>>>>
>>>>       pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
>>>> -                     _get_rate("div_arm2"));
>>>> +                     _get_rate("armclk"));
>>>
>>> Similarly here, no need for this change.
>>
>> Same here. Instead of getting the rate from div_core2 divider block,
>> the cpu clock instance is used to find the rate. I would prefer to use
>> cpu clock here. Is there any reason to prefer div_core2 over the cpu
>> clock instance?
>
> Well, the reason is simple: if you don't need to change something (i.e.
> the change doesn't have any advantages), don't change it.

The advantage with using cpu clock would be that get_rate can obtain
the cached rate whereas when reading div_core2 rate, the clock tree
will have to be traversed to determine the rate.

>
> There is no difference between obtaining the rate from div_{arm,core}2
> and armclk, so I don't see the point of changing this.
>
> In fact now when thinking of it, this has revealed one hole that will be
> unhandled by your code - if cpufreq is disabled and the bootloader
> configures div_{arm,core}{,2} with non-zero values, armclk will return
> incorrect rate. However since I haven't observed such case on existing
> platforms, fixing this might be done on top of this series, in a
> separate patch.

Right. I will fix this later.

Thanks,
Thomas.

>
> Best regards,
> Tomasz
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Tomasz Figa July 31, 2014, 6:46 p.m. | #5
On 31.07.2014 20:41, Thomas Abraham wrote:
> On Fri, Aug 1, 2014 at 12:05 AM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
>> On 31.07.2014 20:24, Thomas Abraham wrote:
>>> Hi Tomasz,
>>>
>>> On Thu, Jul 31, 2014 at 7:43 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
>>>> On 30.07.2014 10:07, Thomas Abraham wrote:
>>>>> With some of the Exynos SoCs switched over to use the generic CPUfreq drivers,
>>>>> the unused clock aliases can be removed. In addition to this, the individual
>>>>> clock blocks which are now encapsulated with the consolidate CPU clock type
>>>>> can now be marked with read-only flags.
>>>>
>>>> [snip]
>>>>
>>>>> @@ -1500,6 +1499,7 @@ static void __init exynos4_clk_init(struct device_node *np,
>>>>>               exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
>>>>>               _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
>>>>>               _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
>>>>> +             exynos4_soc == EXYNOS4210 ? _get_rate("armclk") :
>>>>>               _get_rate("div_core2"));
>>>>
>>>> I believe "div_core2" should work fine here for all SoCs without the
>>>> need for this if.
>>>
>>> The following patch is a pre-requisite for this patch.
>>> http://www.spinics.net/lists/arm-kernel/msg351540.html
>>>
>>> The rate can be obtained from div_core2 as well but with the cpu clock
>>> now registered, the rate can be obtained from the cpu clock instance
>>> instead of the div_core2 divider. And when Exynos4412 also add cpu
>>> clock instance, the 'if' above will be removed.
>>>
>>>>
>>>>>  }
>>>>>
>>>>> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
>>>>> index e19e365..1d958f1 100644
>>>>> --- a/drivers/clk/samsung/clk-exynos5250.c
>>>>> +++ b/drivers/clk/samsung/clk-exynos5250.c
>>>>
>>>> [snip]
>>>>
>>>>> @@ -848,6 +851,6 @@ static void __init exynos5250_clk_init(struct device_node *np)
>>>>>       samsung_clk_of_add_provider(np, ctx);
>>>>>
>>>>>       pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
>>>>> -                     _get_rate("div_arm2"));
>>>>> +                     _get_rate("armclk"));
>>>>
>>>> Similarly here, no need for this change.
>>>
>>> Same here. Instead of getting the rate from div_core2 divider block,
>>> the cpu clock instance is used to find the rate. I would prefer to use
>>> cpu clock here. Is there any reason to prefer div_core2 over the cpu
>>> clock instance?
>>
>> Well, the reason is simple: if you don't need to change something (i.e.
>> the change doesn't have any advantages), don't change it.
> 
> The advantage with using cpu clock would be that get_rate can obtain
> the cached rate whereas when reading div_core2 rate, the clock tree
> will have to be traversed to determine the rate.
> 

This is just one time printk at initialization, so still no real
benefits. :)

Well anyway, if you really don't want to undo this change, then I guess
I can live with it.

Best regards,
Tomasz
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Thomas Abraham July 31, 2014, 6:49 p.m. | #6
On Fri, Aug 1, 2014 at 12:16 AM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
> On 31.07.2014 20:41, Thomas Abraham wrote:
>> On Fri, Aug 1, 2014 at 12:05 AM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
>>> On 31.07.2014 20:24, Thomas Abraham wrote:
>>>> Hi Tomasz,
>>>>
>>>> On Thu, Jul 31, 2014 at 7:43 PM, Tomasz Figa <tomasz.figa@gmail.com> wrote:
>>>>> On 30.07.2014 10:07, Thomas Abraham wrote:
>>>>>> With some of the Exynos SoCs switched over to use the generic CPUfreq drivers,
>>>>>> the unused clock aliases can be removed. In addition to this, the individual
>>>>>> clock blocks which are now encapsulated with the consolidate CPU clock type
>>>>>> can now be marked with read-only flags.
>>>>>
>>>>> [snip]
>>>>>
>>>>>> @@ -1500,6 +1499,7 @@ static void __init exynos4_clk_init(struct device_node *np,
>>>>>>               exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
>>>>>>               _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
>>>>>>               _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
>>>>>> +             exynos4_soc == EXYNOS4210 ? _get_rate("armclk") :
>>>>>>               _get_rate("div_core2"));
>>>>>
>>>>> I believe "div_core2" should work fine here for all SoCs without the
>>>>> need for this if.
>>>>
>>>> The following patch is a pre-requisite for this patch.
>>>> http://www.spinics.net/lists/arm-kernel/msg351540.html
>>>>
>>>> The rate can be obtained from div_core2 as well but with the cpu clock
>>>> now registered, the rate can be obtained from the cpu clock instance
>>>> instead of the div_core2 divider. And when Exynos4412 also add cpu
>>>> clock instance, the 'if' above will be removed.
>>>>
>>>>>
>>>>>>  }
>>>>>>
>>>>>> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
>>>>>> index e19e365..1d958f1 100644
>>>>>> --- a/drivers/clk/samsung/clk-exynos5250.c
>>>>>> +++ b/drivers/clk/samsung/clk-exynos5250.c
>>>>>
>>>>> [snip]
>>>>>
>>>>>> @@ -848,6 +851,6 @@ static void __init exynos5250_clk_init(struct device_node *np)
>>>>>>       samsung_clk_of_add_provider(np, ctx);
>>>>>>
>>>>>>       pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
>>>>>> -                     _get_rate("div_arm2"));
>>>>>> +                     _get_rate("armclk"));
>>>>>
>>>>> Similarly here, no need for this change.
>>>>
>>>> Same here. Instead of getting the rate from div_core2 divider block,
>>>> the cpu clock instance is used to find the rate. I would prefer to use
>>>> cpu clock here. Is there any reason to prefer div_core2 over the cpu
>>>> clock instance?
>>>
>>> Well, the reason is simple: if you don't need to change something (i.e.
>>> the change doesn't have any advantages), don't change it.
>>
>> The advantage with using cpu clock would be that get_rate can obtain
>> the cached rate whereas when reading div_core2 rate, the clock tree
>> will have to be traversed to determine the rate.
>>
>
> This is just one time printk at initialization, so still no real
> benefits. :)
>
> Well anyway, if you really don't want to undo this change, then I guess
> I can live with it.

Thanks Tomasz. Probably, I would just use cpu clock for now.

>
> Best regards,
> Tomasz
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Mike Turquette Sept. 1, 2014, 10:31 p.m. | #7
Quoting Thomas Abraham (2014-07-30 01:07:43)
> With some of the Exynos SoCs switched over to use the generic CPUfreq drivers,
> the unused clock aliases can be removed. In addition to this, the individual
> clock blocks which are now encapsulated with the consolidate CPU clock type
> can now be marked with read-only flags.
> 
> Cc: Tomasz Figa <t.figa@samsung.com>
> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>

Acked-by: Mike Turquette <mturquette@linaro.org>

> ---
>  drivers/clk/samsung/clk-exynos4.c    |   48 +++++++++++++++++-----------------
>  drivers/clk/samsung/clk-exynos5250.c |   19 ++++++++------
>  drivers/clk/samsung/clk-exynos5420.c |   27 ++++++++++++-------
>  3 files changed, 53 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
> index 101f549..04619a1 100644
> --- a/drivers/clk/samsung/clk-exynos4.c
> +++ b/drivers/clk/samsung/clk-exynos4.c
> @@ -578,7 +578,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
>         MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
>         MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
>         MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
> -       MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
> +       MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1, 0,
> +                       CLK_MUX_READ_ONLY),
>         MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1),
>         MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
>         MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
> @@ -714,15 +715,24 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
>         DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
>                         CLKOUT_CMU_RIGHTBUS, 8, 6),
>  
> -       DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
> -       DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
> -       DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
> -       DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
> -       DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
> -       DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
> -       DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3),
> -       DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
> -       DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
> +       DIV_F(0, "div_core", "mout_core", DIV_CPU0, 0, 3,
> +                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
> +       DIV_F(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3,
> +                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
> +       DIV_F(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3,
> +                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
> +       DIV_F(0, "div_periph", "div_core2", DIV_CPU0, 12, 3,
> +                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
> +       DIV_F(0, "div_atb", "mout_core", DIV_CPU0, 16, 3,
> +                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
> +       DIV_F(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3,
> +                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
> +       DIV_F(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3,
> +                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
> +       DIV_F(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3,
> +                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
> +       DIV_F(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3,
> +                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
>         DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
>  
>         DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
> @@ -770,7 +780,8 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
>         DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
>         DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
>         DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
> -       DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
> +       DIV_F(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3,
> +                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
>         DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
>                         CLK_SET_RATE_PARENT, 0),
>         DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
> @@ -1187,17 +1198,10 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
>                 0),
>  };
>  
> -static struct samsung_clock_alias exynos4_aliases[] __initdata = {
> +static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
>         ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),
>         ALIAS(CLK_ARM_CLK, NULL, "armclk"),
>         ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),
> -};
> -
> -static struct samsung_clock_alias exynos4210_aliases[] __initdata = {
> -       ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),
> -};
> -
> -static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
>         ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),
>  };
>  
> @@ -1464,8 +1468,6 @@ static void __init exynos4_clk_init(struct device_node *np,
>                         ARRAY_SIZE(exynos4210_div_clks));
>                 samsung_clk_register_gate(ctx, exynos4210_gate_clks,
>                         ARRAY_SIZE(exynos4210_gate_clks));
> -               samsung_clk_register_alias(ctx, exynos4210_aliases,
> -                       ARRAY_SIZE(exynos4210_aliases));
>                 samsung_clk_register_fixed_factor(ctx,
>                         exynos4210_fixed_factor_clks,
>                         ARRAY_SIZE(exynos4210_fixed_factor_clks));
> @@ -1487,9 +1489,6 @@ static void __init exynos4_clk_init(struct device_node *np,
>                         ARRAY_SIZE(exynos4x12_fixed_factor_clks));
>         }
>  
> -       samsung_clk_register_alias(ctx, exynos4_aliases,
> -                       ARRAY_SIZE(exynos4_aliases));
> -
>         exynos4_core_down_clock(soc);
>         exynos4_clk_sleep_init();
>  
> @@ -1500,6 +1499,7 @@ static void __init exynos4_clk_init(struct device_node *np,
>                 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
>                 _get_rate("sclk_apll"), _get_rate("sclk_mpll"),
>                 _get_rate("sclk_epll"), _get_rate("sclk_vpll"),
> +               exynos4_soc == EXYNOS4210 ? _get_rate("armclk") :
>                 _get_rate("div_core2"));
>  }
>  
> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
> index e19e365..1d958f1 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -291,14 +291,14 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
>         /*
>          * CMU_CPU
>          */
> -       MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
> -                                       CLK_SET_RATE_PARENT, 0, "mout_apll"),
> -       MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
> +       MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
> +                       CLK_SET_RATE_PARENT, 0),
> +       MUX_F(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, 0, CLK_MUX_READ_ONLY),
>  
>         /*
>          * CMU_CORE
>          */
> -       MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
> +       MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
>  
>         /*
>          * CMU_TOP
> @@ -380,9 +380,12 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
>         /*
>          * CMU_CPU
>          */
> -       DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
> -       DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
> -       DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),
> +       DIV_F(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3,
> +                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
> +       DIV_F(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3,
> +                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
> +       DIV_F(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3,
> +                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
>  
>         /*
>          * CMU_TOP
> @@ -848,6 +851,6 @@ static void __init exynos5250_clk_init(struct device_node *np)
>         samsung_clk_of_add_provider(np, ctx);
>  
>         pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
> -                       _get_rate("div_arm2"));
> +                       _get_rate("armclk"));
>  }
>  CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index d7ef36a..fcf365d 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -617,10 +617,14 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
>         MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
>         MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
>  
> -       MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
> -       MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
> -       MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
> -       MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
> +       MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
> +                               CLK_SET_RATE_PARENT, 0),
> +       MUX_F(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, 0,
> +                               CLK_MUX_READ_ONLY),
> +       MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
> +                               CLK_SET_RATE_PARENT, 0),
> +       MUX_F(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1, 0,
> +                               CLK_MUX_READ_ONLY),
>  
>         MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
>         MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
> @@ -776,11 +780,16 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
>  };
>  
>  static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
> -       DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
> -       DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
> -       DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
> -       DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
> -       DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
> +       DIV_F(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3,
> +                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
> +       DIV_F(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3,
> +                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
> +       DIV_F(0, "armclk2", "div_arm", DIV_CPU0, 28, 3,
> +                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
> +       DIV_F(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3,
> +                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
> +       DIV_F(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3,
> +                       CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
>  
>         DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),
>         DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
> -- 
> 1.7.9.5
> 
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Patch

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 101f549..04619a1 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -578,7 +578,8 @@  static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
 	MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
 	MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
 	MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
-	MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
+	MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1, 0,
+			CLK_MUX_READ_ONLY),
 	MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1),
 	MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
 	MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
@@ -714,15 +715,24 @@  static struct samsung_div_clock exynos4_div_clks[] __initdata = {
 	DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
 			CLKOUT_CMU_RIGHTBUS, 8, 6),
 
-	DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
-	DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
-	DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
-	DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
-	DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
-	DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
-	DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3),
-	DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
-	DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
+	DIV_F(0, "div_core", "mout_core", DIV_CPU0, 0, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_periph", "div_core2", DIV_CPU0, 12, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_atb", "mout_core", DIV_CPU0, 16, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
 	DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
 
 	DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
@@ -770,7 +780,8 @@  static struct samsung_div_clock exynos4_div_clks[] __initdata = {
 	DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
 	DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
 	DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
-	DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
+	DIV_F(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
 	DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
 			CLK_SET_RATE_PARENT, 0),
 	DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
@@ -1187,17 +1198,10 @@  static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
 		0),
 };
 
-static struct samsung_clock_alias exynos4_aliases[] __initdata = {
+static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
 	ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),
 	ALIAS(CLK_ARM_CLK, NULL, "armclk"),
 	ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),
-};
-
-static struct samsung_clock_alias exynos4210_aliases[] __initdata = {
-	ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),
-};
-
-static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
 	ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),
 };
 
@@ -1464,8 +1468,6 @@  static void __init exynos4_clk_init(struct device_node *np,
 			ARRAY_SIZE(exynos4210_div_clks));
 		samsung_clk_register_gate(ctx, exynos4210_gate_clks,
 			ARRAY_SIZE(exynos4210_gate_clks));
-		samsung_clk_register_alias(ctx, exynos4210_aliases,
-			ARRAY_SIZE(exynos4210_aliases));
 		samsung_clk_register_fixed_factor(ctx,
 			exynos4210_fixed_factor_clks,
 			ARRAY_SIZE(exynos4210_fixed_factor_clks));
@@ -1487,9 +1489,6 @@  static void __init exynos4_clk_init(struct device_node *np,
 			ARRAY_SIZE(exynos4x12_fixed_factor_clks));
 	}
 
-	samsung_clk_register_alias(ctx, exynos4_aliases,
-			ARRAY_SIZE(exynos4_aliases));
-
 	exynos4_core_down_clock(soc);
 	exynos4_clk_sleep_init();
 
@@ -1500,6 +1499,7 @@  static void __init exynos4_clk_init(struct device_node *np,
 		exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
 		_get_rate("sclk_apll"),	_get_rate("sclk_mpll"),
 		_get_rate("sclk_epll"), _get_rate("sclk_vpll"),
+		exynos4_soc == EXYNOS4210 ? _get_rate("armclk") :
 		_get_rate("div_core2"));
 }
 
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index e19e365..1d958f1 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -291,14 +291,14 @@  static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
 	/*
 	 * CMU_CPU
 	 */
-	MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
-					CLK_SET_RATE_PARENT, 0, "mout_apll"),
-	MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
+	MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+			CLK_SET_RATE_PARENT, 0),
+	MUX_F(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, 0, CLK_MUX_READ_ONLY),
 
 	/*
 	 * CMU_CORE
 	 */
-	MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
+	MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
 
 	/*
 	 * CMU_TOP
@@ -380,9 +380,12 @@  static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
 	/*
 	 * CMU_CPU
 	 */
-	DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
-	DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
-	DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),
+	DIV_F(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
 
 	/*
 	 * CMU_TOP
@@ -848,6 +851,6 @@  static void __init exynos5250_clk_init(struct device_node *np)
 	samsung_clk_of_add_provider(np, ctx);
 
 	pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
-			_get_rate("div_arm2"));
+			_get_rate("armclk"));
 }
 CLK_OF_DECLARE(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index d7ef36a..fcf365d 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -617,10 +617,14 @@  static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
 	MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
 	MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
 
-	MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
-	MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
-	MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
-	MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
+	MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+				CLK_SET_RATE_PARENT, 0),
+	MUX_F(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, 0,
+				CLK_MUX_READ_ONLY),
+	MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
+				CLK_SET_RATE_PARENT, 0),
+	MUX_F(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1, 0,
+				CLK_MUX_READ_ONLY),
 
 	MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
 	MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
@@ -776,11 +780,16 @@  static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
 };
 
 static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
-	DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
-	DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
-	DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
-	DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
-	DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
+	DIV_F(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "armclk2", "div_arm", DIV_CPU0, 28, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+	DIV_F(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
 
 	DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),
 	DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),