From patchwork Wed Aug 13 13:12:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Omair Javaid X-Patchwork-Id: 35356 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-oa0-f72.google.com (mail-oa0-f72.google.com [209.85.219.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 2EC4D203C5 for ; Wed, 13 Aug 2014 13:13:39 +0000 (UTC) Received: by mail-oa0-f72.google.com with SMTP id m1sf53356280oag.3 for ; Wed, 13 Aug 2014 06:13:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=pCA3SuHVITKyH1gM4YsnVFHR636YJPdfoAWiW0GgFZA=; b=jQTlagOKOblGUEkjkIAymMTjfJA132YK6+pYXPzqaPaXL1MLv9xEVpBKstcJU0jZZI wh0dPfyY2WJ3VXnUu/5H4PRHwH5lMVuOwJQ/SwbbKexceUwDTDChHa/1ckXNP1WGsHDP F6raFtou7B7O3KsXGKw3+tCCy/l1jEpf2mzcg/Q7H9z38Q/1HpBA4TXT9o/LQVOB8Zup vnRV3GMz/QjwW2V9KYSTSmqdAURcmFyZ7hYNPTy8y0OT5FW1acc5MpIYLdwK74SAJG8T 0tCYsm2P8x7kDJpPsRUeCrMJwJ5LyS5xRtoKTVtsQCp2jWxpO+sH9NbNxjqdfOAjgilJ zX4g== X-Gm-Message-State: ALoCoQlJJuxNNJzB6WmLSn7R3oxiHsYdJC4bCcckwIxWJnSunsnTzS3wMt/tZNyANFZRyIoHU5SA X-Received: by 10.50.80.111 with SMTP id q15mr2513939igx.0.1407935618807; Wed, 13 Aug 2014 06:13:38 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.38.176 with SMTP id t45ls553161qgt.60.gmail; Wed, 13 Aug 2014 06:13:38 -0700 (PDT) X-Received: by 10.52.165.129 with SMTP id yy1mr713313vdb.57.1407935618591; Wed, 13 Aug 2014 06:13:38 -0700 (PDT) Received: from mail-vc0-f169.google.com (mail-vc0-f169.google.com [209.85.220.169]) by mx.google.com with ESMTPS id re13si1078548vcb.8.2014.08.13.06.13.38 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 13 Aug 2014 06:13:38 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.169 as permitted sender) client-ip=209.85.220.169; Received: by mail-vc0-f169.google.com with SMTP id le20so15050080vcb.14 for ; Wed, 13 Aug 2014 06:13:38 -0700 (PDT) X-Received: by 10.52.120.51 with SMTP id kz19mr362081vdb.95.1407935618504; Wed, 13 Aug 2014 06:13:38 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp329772vcb; Wed, 13 Aug 2014 06:13:37 -0700 (PDT) X-Received: by 10.195.13.34 with SMTP id ev2mr4250376wjd.55.1407935617398; Wed, 13 Aug 2014 06:13:37 -0700 (PDT) Received: from mail-wi0-f171.google.com (mail-wi0-f171.google.com [209.85.212.171]) by mx.google.com with ESMTPS id o1si26034540wiy.46.2014.08.13.06.13.36 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 13 Aug 2014 06:13:37 -0700 (PDT) Received-SPF: pass (google.com: domain of omair.javaid@linaro.org designates 209.85.212.171 as permitted sender) client-ip=209.85.212.171; Received: by mail-wi0-f171.google.com with SMTP id hi2so7378822wib.10 for ; Wed, 13 Aug 2014 06:13:36 -0700 (PDT) X-Received: by 10.194.142.200 with SMTP id ry8mr4428023wjb.37.1407935616904; Wed, 13 Aug 2014 06:13:36 -0700 (PDT) Received: from localhost.localdomain ([182.185.185.192]) by mx.google.com with ESMTPSA id w14sm50806711wij.2.2014.08.13.06.13.34 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 Aug 2014 06:13:36 -0700 (PDT) From: Omair Javaid To: gdb-patches@sourceware.org Cc: patches@linaro.org Subject: [PATCH v3 4/6] Implement support for recording extension register ld/st insn Date: Wed, 13 Aug 2014 18:12:13 +0500 Message-Id: <1407935535-27978-5-git-send-email-omair.javaid@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1407935535-27978-1-git-send-email-omair.javaid@linaro.org> References: <1407935535-27978-1-git-send-email-omair.javaid@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: omair.javaid@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.169 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , gdb: 2014-08-13 Omair Javaid * arm-tdep.c (arm_record_asimd_vfp_coproc): Updated. (arm_record_exreg_ld_st_insn): Added record handler for ex-register load/store instructions. --- gdb/arm-tdep.c | 167 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 165 insertions(+), 2 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index d003619..315b5b0 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -11990,6 +11990,169 @@ arm_record_unsupported_insn (insn_decode_record *arm_insn_r) return -1; } +/* Record handler for extension register load/store instructions. */ + +static int +arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r) +{ + uint32_t opcode, single_reg; + uint8_t op_vldm_vstm; + uint32_t record_buf[8], record_buf_mem[128]; + ULONGEST u_regval = 0; + + struct regcache *reg_cache = arm_insn_r->regcache; + const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch); + + opcode = bits (arm_insn_r->arm_insn, 20, 24); + single_reg = bit (arm_insn_r->arm_insn, 8); + op_vldm_vstm = opcode & 0x1b; + + /* Handle VMOV instructions. */ + if ((opcode & 0x1e) == 0x04) + { + if (bit (arm_insn_r->arm_insn, 4)) + { + record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); + record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); + arm_insn_r->reg_rec_count = 2; + } + else + { + uint8_t reg_m = (bits (arm_insn_r->arm_insn, 0, 3) << 1) + | bit (arm_insn_r->arm_insn, 5); + + if (!single_reg) + { + record_buf[0] = num_regs + reg_m; + record_buf[1] = num_regs + reg_m + 1; + arm_insn_r->reg_rec_count = 2; + } + else + { + record_buf[0] = reg_m + ARM_D0_REGNUM; + arm_insn_r->reg_rec_count = 1; + } + } + } + /* Handle VSTM and VPUSH instructions. */ + else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a + || op_vldm_vstm == 0x12) + { + uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count; + uint32_t memory_index = 0; + + reg_rn = bits (arm_insn_r->arm_insn, 16, 19); + regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); + imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); + imm_off32 = imm_off8 << 24; + memory_count = imm_off8; + + if (bit (arm_insn_r->arm_insn, 23)) + start_address = u_regval; + else + start_address = u_regval - imm_off32; + + if (bit (arm_insn_r->arm_insn, 21)) + { + record_buf[0] = reg_rn; + arm_insn_r->reg_rec_count = 1; + } + + while (memory_count) + { + if (!single_reg) + { + record_buf_mem[memory_index] = start_address; + record_buf_mem[memory_index + 1] = 4; + start_address = start_address + 4; + memory_index = memory_index + 2; + } + else + { + record_buf_mem[memory_index] = start_address; + record_buf_mem[memory_index + 1] = 4; + record_buf_mem[memory_index + 2] = start_address + 4; + record_buf_mem[memory_index + 3] = 4; + start_address = start_address + 8; + memory_index = memory_index + 4; + } + memory_count--; + } + } + /* Handle VLDM instructions. */ + else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b + || op_vldm_vstm == 0x13) + { + uint32_t reg_count, reg_vd; + uint32_t reg_index = 0; + + reg_vd = bits (arm_insn_r->arm_insn, 12, 15); + reg_count = bits (arm_insn_r->arm_insn, 0, 7); + + if (single_reg) + reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 0) << 4); + else + reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 0); + + if (bit (arm_insn_r->arm_insn, 21)) + record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19); + + while (reg_count) + { + if (single_reg) + record_buf[reg_index++] = num_regs + reg_vd + reg_count - 1; + else + record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1; + + reg_count--; + } + } + /* VSTR Vector store register. */ + else if ((opcode & 0x13) == 0x10) + { + uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count; + uint32_t memory_index = 0; + + reg_rn = bits (arm_insn_r->arm_insn, 16, 19); + regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); + imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); + imm_off32 = imm_off8 << 24; + memory_count = imm_off8; + + if (bit (arm_insn_r->arm_insn, 23)) + start_address = u_regval + imm_off32; + else + start_address = u_regval - imm_off32; + + if (single_reg) + { + record_buf_mem[memory_index] = start_address; + record_buf_mem[memory_index + 1] = 4; + } + else + { + record_buf_mem[memory_index] = start_address; + record_buf_mem[memory_index + 1] = 4; + record_buf_mem[memory_index + 2] = start_address + 4; + record_buf_mem[memory_index + 3] = 4; + } + } + /* VLDR Vector load register. */ + else if ((opcode & 0x13) == 0x11) + { + uint8_t single_reg = 0; + uint8_t special_case; + + record_buf[0] = 0; + record_buf[1] = 0; + arm_insn_r->reg_rec_count = 2; + } + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); + return 0; +} + /* Record handler for arm/thumb mode VFP data processing instructions. */ static int @@ -12218,11 +12381,11 @@ arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r) { /* Handle extension register ld/st instructions. */ if (!(op1 & 0x20)) - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_exreg_ld_st_insn (arm_insn_r); /* 64-bit transfers between arm core and extension registers. */ if ((op1 & 0x3e) == 0x04) - return arm_record_unsupported_insn (arm_insn_r); + return arm_record_exreg_ld_st_insn (arm_insn_r); } else {