| Message ID | 1408471784-2652-1-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | Not Applicable |
| Headers | show |
On 19 August 2014 19:09, Peter Maydell <peter.maydell@linaro.org> wrote: > Flushing my queue of reviewed ARM patches: single step, > plus a collection of straightforward patches from other > people. > > thanks > -- PMM > > > The following changes since commit 0e4a77370594c91dd126f9872893ed473374cc72: > > Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2014-08-19 13:00:57 +0100) > > are available in the git repository at: > > > git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140819 > > for you to fetch changes up to 14a906f755f77b325666d67e071c572478d06067: > > arm: stellaris: Remove misleading address_space_mem var (2014-08-19 19:02:40 +0100) > > ---------------------------------------------------------------- > target-arm: > * fix preferred return address for A64 BRK insn > * implement AArch64 single-stepping > * support loading gzip compressed AArch64 kernels > * use correct PSCI function IDs in the DT when KVM uses PSCI 0.2 > * minor cleanups > > ---------------------------------------------------------------- > Christoffer Dall (2): > target-arm: Rename QEMU PSCI v0.1 definitions > arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2 > > Peter Crosthwaite (3): > arm: cortex-a9: Fix cache-line size and associativity > arm: armv7m: Rename address_space_mem -> system_memory > arm: stellaris: Remove misleading address_space_mem var > > Peter Maydell (12): > target-arm: Fix return address for A64 BRK instructions > target-arm: Collect up the debug cp register definitions > target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14 > target-arm: Provide both 32 and 64 bit versions of debug registers > target-arm: Adjust debug ID registers per-CPU > target-arm: Don't allow AArch32 to access RES0 CPSR bits > target-arm: Correctly handle PSTATE.SS when taking exception to AArch32 > target-arm: Set PSTATE.SS correctly on exception return from AArch64 > target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tb > target-arm: Implement ARMv8 single-step handling for A64 code > target-arm: Implement ARMv8 single-stepping for AArch32 code > target-arm: Implement MDSCR_EL1 as having state > > Richard W.M. Jones (2): > loader: Add load_image_gzipped function. > aarch64: Allow -kernel option to take a gzip-compressed kernel. Applied, thanks. -- PMM
Flushing my queue of reviewed ARM patches: single step, plus a collection of straightforward patches from other people. thanks -- PMM The following changes since commit 0e4a77370594c91dd126f9872893ed473374cc72: Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2014-08-19 13:00:57 +0100) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20140819 for you to fetch changes up to 14a906f755f77b325666d67e071c572478d06067: arm: stellaris: Remove misleading address_space_mem var (2014-08-19 19:02:40 +0100) ---------------------------------------------------------------- target-arm: * fix preferred return address for A64 BRK insn * implement AArch64 single-stepping * support loading gzip compressed AArch64 kernels * use correct PSCI function IDs in the DT when KVM uses PSCI 0.2 * minor cleanups ---------------------------------------------------------------- Christoffer Dall (2): target-arm: Rename QEMU PSCI v0.1 definitions arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2 Peter Crosthwaite (3): arm: cortex-a9: Fix cache-line size and associativity arm: armv7m: Rename address_space_mem -> system_memory arm: stellaris: Remove misleading address_space_mem var Peter Maydell (12): target-arm: Fix return address for A64 BRK instructions target-arm: Collect up the debug cp register definitions target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14 target-arm: Provide both 32 and 64 bit versions of debug registers target-arm: Adjust debug ID registers per-CPU target-arm: Don't allow AArch32 to access RES0 CPSR bits target-arm: Correctly handle PSTATE.SS when taking exception to AArch32 target-arm: Set PSTATE.SS correctly on exception return from AArch64 target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tb target-arm: Implement ARMv8 single-step handling for A64 code target-arm: Implement ARMv8 single-stepping for AArch32 code target-arm: Implement MDSCR_EL1 as having state Richard W.M. Jones (2): loader: Add load_image_gzipped function. aarch64: Allow -kernel option to take a gzip-compressed kernel. hw/arm/armv7m.c | 8 +-- hw/arm/boot.c | 7 +++ hw/arm/stellaris.c | 3 +- hw/arm/virt.c | 31 ++++++++-- hw/core/loader.c | 48 +++++++++++++++ include/hw/arm/arm.h | 2 +- include/hw/loader.h | 1 + target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 7 ++- target-arm/cpu.h | 115 ++++++++++++++++++++++++++++++++++- target-arm/cpu64.c | 1 + target-arm/helper.c | 145 +++++++++++++++++++++++++++++++-------------- target-arm/helper.h | 1 + target-arm/internals.h | 6 ++ target-arm/kvm-consts.h | 49 +++++++++++---- target-arm/op_helper.c | 27 ++++++++- target-arm/translate-a64.c | 98 +++++++++++++++++++++++++++--- target-arm/translate.c | 89 +++++++++++++++++++++++++--- target-arm/translate.h | 12 ++++ 19 files changed, 563 insertions(+), 88 deletions(-)