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[199.106.103.253]) by mx.google.com with ESMTPSA id zq5sm20305897pbb.37.2014.08.19.15.16.06 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Aug 2014 15:16:08 -0700 (PDT) From: Lina Iyer To: daniel.lezcano@linaro.org, khilman@linaro.org, sboyd@codeaurora.org, davidb@codeaurora.org, galak@codeaurora.org, linux-arm-msm@vger.kernel.org, lorenzo.pieralisi@arm.com Cc: msivasub@codeaurora.org, Lina Iyer Subject: [PATCH v4 8/8] arm: dts: qcom: Add idle states device nodes for 8974 Date: Tue, 19 Aug 2014 16:15:37 -0600 Message-Id: <1408486537-6358-9-git-send-email-lina.iyer@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1408486537-6358-1-git-send-email-lina.iyer@linaro.org> References: <1408486537-6358-1-git-send-email-lina.iyer@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: lina.iyer@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.177 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add allowable C-States for each cpu using the cpu-idle-states node. ARM spec dictates WFI as the default idle state at 0. Support standalone power collapse (power down that does not affect any SoC idle states) for each cpu. Signed-off-by: Lina Iyer --- arch/arm/boot/dts/qcom-msm8974.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 0580bc2..fd66afb 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -21,6 +21,7 @@ reg = <0>; next-level-cache = <&L2>; qcom,acc = <&acc0>; + cpu-idle-states = <&CPU_SPC>; }; CPU1: cpu@1 { @@ -30,6 +31,7 @@ reg = <1>; next-level-cache = <&L2>; qcom,acc = <&acc1>; + cpu-idle-states = <&CPU_SPC>; }; CPU2: cpu@2 { @@ -39,6 +41,7 @@ reg = <2>; next-level-cache = <&L2>; qcom,acc = <&acc2>; + cpu-idle-states = <&CPU_SPC>; }; CPU3: cpu@3 { @@ -48,6 +51,7 @@ reg = <3>; next-level-cache = <&L2>; qcom,acc = <&acc3>; + cpu-idle-states = <&CPU_SPC>; }; L2: l2-cache { @@ -55,6 +59,16 @@ cache-level = <2>; qcom,saw = <&saw_l2>; }; + + idle-states { + CPU_SPC: cpu-sleep-0 { + compatible = "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + entry-method = "standalone-pc"; + }; + }; }; cpu-pmu {