diff mbox series

[v2] arm64: dts: imx8mq: Add clock parents for mipi dphy

Message ID bc2da4ab8322d5e8a44018633e0220e08d70e72e.1610297714.git.agx@sigxcpu.org
State Accepted
Commit 62270eeb2b639ed840ee133e301073057d497ed8
Headers show
Series [v2] arm64: dts: imx8mq: Add clock parents for mipi dphy | expand

Commit Message

Guido Günther Jan. 10, 2021, 4:55 p.m. UTC
This makes sure the clock tree setup for the dphy is not dependent on
other components.

Without this change bringing up the display can fail like

  kernel: phy phy-30a00300.dphy.2: Invalid CM/CN/CO values: 165/217/1
  kernel: phy phy-30a00300.dphy.2: for hs_clk/ref_clk=451656000/593999998 ~ 165/217

if LCDIF doesn't set up that part of the clock tree first. This was
noticed when testing the Librem 5 devkit with defconfig. It doesn't
happen when modules are built in.

Signed-off-by: Guido Günther <agx@sigxcpu.org>

---
Changes from v1:
- as per review comment from Shawn Guo
  https://lore.kernel.org/linux-arm-kernel/20210110124629.GO28365@dragon/
  Set clock rate for IMX8MQ_VIDEO_PLL1 too. Otherwise we end up with
  a close but not exact clock rate.

 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

Comments

Shawn Guo Jan. 11, 2021, 12:25 a.m. UTC | #1
On Sun, Jan 10, 2021 at 05:55:51PM +0100, Guido Günther wrote:
> This makes sure the clock tree setup for the dphy is not dependent on

> other components.

> 

> Without this change bringing up the display can fail like

> 

>   kernel: phy phy-30a00300.dphy.2: Invalid CM/CN/CO values: 165/217/1

>   kernel: phy phy-30a00300.dphy.2: for hs_clk/ref_clk=451656000/593999998 ~ 165/217

> 

> if LCDIF doesn't set up that part of the clock tree first. This was

> noticed when testing the Librem 5 devkit with defconfig. It doesn't

> happen when modules are built in.

> 

> Signed-off-by: Guido Günther <agx@sigxcpu.org>


Applied, thanks.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index a841a023e8e0..50ae17f65a51 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1016,9 +1016,14 @@  dphy: dphy@30a00300 {
 				reg = <0x30a00300 0x100>;
 				clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
 				clock-names = "phy_ref";
-				assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
-				assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
-				assigned-clock-rates = <24000000>;
+				assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
+						  <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
+						  <&clk IMX8MQ_CLK_DSI_PHY_REF>,
+						  <&clk IMX8MQ_VIDEO_PLL1>;
+				assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
+						  <&clk IMX8MQ_VIDEO_PLL1>,
+						  <&clk IMX8MQ_VIDEO_PLL1_OUT>;
+				assigned-clock-rates = <0>, <0>, <24000000>, <594000000>;
 				#phy-cells = <0>;
 				power-domains = <&pgc_mipi>;
 				status = "disabled";