diff mbox series

[v2,07/11] clk: qcom: mmcc-msm8998: Set CLK_GET_RATE_NOCACHE to pixel/byte clks

Message ID 20210114221059.483390-8-angelogioacchino.delregno@somainline.org
State New
Headers show
Series Clock fixes for MSM8998 GCC, MMCC, GPUCC | expand

Commit Message

AngeloGioacchino Del Regno Jan. 14, 2021, 10:10 p.m. UTC
The pixel and byte clocks rate should not be cached, as a VCO shutdown
may clear the frequency setup and this may not be set again due to the
cached rate being present.
This will also be useful when shadow clocks will be implemented in
the DSI PLL for seamless timing/resolution switch.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
---
 drivers/clk/qcom/mmcc-msm8998.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Stephen Boyd Feb. 8, 2021, 6:20 p.m. UTC | #1
Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:55)
> The pixel and byte clocks rate should not be cached, as a VCO shutdown

> may clear the frequency setup and this may not be set again due to the

> cached rate being present.

> This will also be useful when shadow clocks will be implemented in

> the DSI PLL for seamless timing/resolution switch.

> 

> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>

> ---


Applied to clk-next
AngeloGioacchino Del Regno Feb. 9, 2021, 1:19 p.m. UTC | #2
Il 08/02/21 19:21, Stephen Boyd ha scritto:
> Quoting AngeloGioacchino Del Regno (2021-01-14 14:10:55)
>> The pixel and byte clocks rate should not be cached, as a VCO shutdown
>> may clear the frequency setup and this may not be set again due to the
>> cached rate being present.
>> This will also be useful when shadow clocks will be implemented in
>> the DSI PLL for seamless timing/resolution switch.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
>> ---
>>   drivers/clk/qcom/mmcc-msm8998.c | 8 ++++----
>>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> We didn't do this on sdm845, so I'm not going to apply this patch. The
> rate caching thing is a problem with the display driver that should be
> fixed some other way vs. setting nocache here.
> 

Ok, I agree.
diff mbox series

Patch

diff --git a/drivers/clk/qcom/mmcc-msm8998.c b/drivers/clk/qcom/mmcc-msm8998.c
index dd68983fe22e..475e00a5fdf4 100644
--- a/drivers/clk/qcom/mmcc-msm8998.c
+++ b/drivers/clk/qcom/mmcc-msm8998.c
@@ -520,7 +520,7 @@  static struct clk_rcg2 byte0_clk_src = {
 		.parent_data = mmss_xo_dsibyte,
 		.num_parents = 4,
 		.ops = &clk_byte2_ops,
-		.flags = CLK_SET_RATE_PARENT,
+		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 	},
 };
 
@@ -533,7 +533,7 @@  static struct clk_rcg2 byte1_clk_src = {
 		.parent_data = mmss_xo_dsibyte,
 		.num_parents = 4,
 		.ops = &clk_byte2_ops,
-		.flags = CLK_SET_RATE_PARENT,
+		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 	},
 };
 
@@ -1084,7 +1084,7 @@  static struct clk_rcg2 pclk0_clk_src = {
 		.parent_data = mmss_xo_dsi0pll_dsi1pll,
 		.num_parents = 4,
 		.ops = &clk_pixel_ops,
-		.flags = CLK_SET_RATE_PARENT,
+		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 	},
 };
 
@@ -1098,7 +1098,7 @@  static struct clk_rcg2 pclk1_clk_src = {
 		.parent_data = mmss_xo_dsi0pll_dsi1pll,
 		.num_parents = 4,
 		.ops = &clk_pixel_ops,
-		.flags = CLK_SET_RATE_PARENT,
+		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 	},
 };