| Message ID | 20210115210456.1053477-12-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg: backend constraints cleanup | expand |
On Fri, 15 Jan 2021 at 21:14, Richard Henderson <richard.henderson@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/sparc/tcg-target-con-str.h | 22 +++++++++++++++++ > tcg/sparc/tcg-target.h | 5 +--- > tcg/sparc/tcg-target.c.inc | 45 +++++----------------------------- > 3 files changed, 29 insertions(+), 43 deletions(-) > create mode 100644 tcg/sparc/tcg-target-con-str.h > > diff --git a/tcg/sparc/tcg-target-con-str.h b/tcg/sparc/tcg-target-con-str.h > new file mode 100644 > index 0000000000..6dc5b95f33 > --- /dev/null > +++ b/tcg/sparc/tcg-target-con-str.h > @@ -0,0 +1,22 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Define Sparc target-specific operand constraints. > + * Copyright (c) 2021 Linaro > + */ > + > +/* > + * Define constraint letters for register sets: > + * REGS(letter, register_mask) > + */ > +REGS('r', 0xffffffff) > +REGS('R', ALL_64) > +REGS('s', 0xffffffff & ~RESERVE_QLDST) > +REGS('S', ALL_64 & ~RESERVE_QLDST) As with s390, I think an ALL_GENERAL_REGS constant would help here. > + > +/* > + * Define constraint letters for constants: > + * CONST(letter, TCG_CT_CONST_* bit set) > + */ > +CONST('I', TCG_CT_CONST_S11) > +CONST('J', TCG_CT_CONST_S13) > +CONST('Z', TCG_CT_CONST_ZERO) > -static const char *target_parse_constraint(TCGArgConstraint *ct, > - const char *ct_str, TCGType type) > -{ > - switch (*ct_str++) { > - case 'r': > - ct->regs = 0xffffffff; > - break; > - case 'R': > - ct->regs = ALL_64; > - break; > - case 'A': /* qemu_ld/st address constraint */ > - ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff; > - reserve_helpers: > - tcg_regset_reset_reg(ct->regs, TCG_REG_O0); > - tcg_regset_reset_reg(ct->regs, TCG_REG_O1); > - tcg_regset_reset_reg(ct->regs, TCG_REG_O2); > - break; The "A" constraint seems to have vanished in the conversion... thanks -- PMM
On 1/19/21 4:58 AM, Peter Maydell wrote: > On Fri, 15 Jan 2021 at 21:14, Richard Henderson > <richard.henderson@linaro.org> wrote: >> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> >> --- >> tcg/sparc/tcg-target-con-str.h | 22 +++++++++++++++++ >> tcg/sparc/tcg-target.h | 5 +--- >> tcg/sparc/tcg-target.c.inc | 45 +++++----------------------------- >> 3 files changed, 29 insertions(+), 43 deletions(-) >> create mode 100644 tcg/sparc/tcg-target-con-str.h >> >> diff --git a/tcg/sparc/tcg-target-con-str.h b/tcg/sparc/tcg-target-con-str.h >> new file mode 100644 >> index 0000000000..6dc5b95f33 >> --- /dev/null >> +++ b/tcg/sparc/tcg-target-con-str.h >> @@ -0,0 +1,22 @@ >> +/* SPDX-License-Identifier: MIT */ >> +/* >> + * Define Sparc target-specific operand constraints. >> + * Copyright (c) 2021 Linaro >> + */ >> + >> +/* >> + * Define constraint letters for register sets: >> + * REGS(letter, register_mask) >> + */ >> +REGS('r', 0xffffffff) >> +REGS('R', ALL_64) >> +REGS('s', 0xffffffff & ~RESERVE_QLDST) >> +REGS('S', ALL_64 & ~RESERVE_QLDST) > > As with s390, I think an ALL_GENERAL_REGS constant would help here. > > >> + >> +/* >> + * Define constraint letters for constants: >> + * CONST(letter, TCG_CT_CONST_* bit set) >> + */ >> +CONST('I', TCG_CT_CONST_S11) >> +CONST('J', TCG_CT_CONST_S13) >> +CONST('Z', TCG_CT_CONST_ZERO) > > >> -static const char *target_parse_constraint(TCGArgConstraint *ct, >> - const char *ct_str, TCGType type) >> -{ >> - switch (*ct_str++) { >> - case 'r': >> - ct->regs = 0xffffffff; >> - break; >> - case 'R': >> - ct->regs = ALL_64; >> - break; >> - case 'A': /* qemu_ld/st address constraint */ >> - ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff; >> - reserve_helpers: >> - tcg_regset_reset_reg(ct->regs, TCG_REG_O0); >> - tcg_regset_reset_reg(ct->regs, TCG_REG_O1); >> - tcg_regset_reset_reg(ct->regs, TCG_REG_O2); >> - break; > > The "A" constraint seems to have vanished in the conversion... Argh. Something that would have been found eventually, but I really want to turn into a build-time error. r~
diff --git a/tcg/sparc/tcg-target-con-str.h b/tcg/sparc/tcg-target-con-str.h new file mode 100644 index 0000000000..6dc5b95f33 --- /dev/null +++ b/tcg/sparc/tcg-target-con-str.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define Sparc target-specific operand constraints. + * Copyright (c) 2021 Linaro + */ + +/* + * Define constraint letters for register sets: + * REGS(letter, register_mask) + */ +REGS('r', 0xffffffff) +REGS('R', ALL_64) +REGS('s', 0xffffffff & ~RESERVE_QLDST) +REGS('S', ALL_64 & ~RESERVE_QLDST) + +/* + * Define constraint letters for constants: + * CONST(letter, TCG_CT_CONST_* bit set) + */ +CONST('I', TCG_CT_CONST_S11) +CONST('J', TCG_CT_CONST_S13) +CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 95ab9af955..5185b00524 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -66,10 +66,6 @@ typedef enum { TCG_REG_I7, } TCGReg; -#define TCG_CT_CONST_S11 0x100 -#define TCG_CT_CONST_S13 0x200 -#define TCG_CT_CONST_ZERO 0x400 - /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_O6 @@ -172,5 +168,6 @@ extern bool use_vis3_instructions; void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); #define TCG_TARGET_NEED_POOL_LABELS +#define TCG_TARGET_CON_STR_H #endif diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 28b5b6559a..ea2b3274d4 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -67,6 +67,10 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { # define SPARC64 0 #endif +#define TCG_CT_CONST_S11 0x100 +#define TCG_CT_CONST_S13 0x200 +#define TCG_CT_CONST_ZERO 0x400 + /* Note that sparcv8plus can only hold 64 bit quantities in %g and %o registers. These are saved manually by the kernel in full 64-bit slots. The %i and %l registers are saved by the register window @@ -79,6 +83,8 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { # define ALL_64 0xffffu #endif +#define RESERVE_QLDST (7u << TCG_REG_O0) /* O0, O1, O2 */ + /* Define some temporary registers. T2 is used for constant generation. */ #define TCG_REG_T1 TCG_REG_G1 #define TCG_REG_T2 TCG_REG_O7 @@ -320,45 +326,6 @@ static bool patch_reloc(tcg_insn_unit *src_rw, int type, return true; } -/* parse target specific constraints */ -static const char *target_parse_constraint(TCGArgConstraint *ct, - const char *ct_str, TCGType type) -{ - switch (*ct_str++) { - case 'r': - ct->regs = 0xffffffff; - break; - case 'R': - ct->regs = ALL_64; - break; - case 'A': /* qemu_ld/st address constraint */ - ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff; - reserve_helpers: - tcg_regset_reset_reg(ct->regs, TCG_REG_O0); - tcg_regset_reset_reg(ct->regs, TCG_REG_O1); - tcg_regset_reset_reg(ct->regs, TCG_REG_O2); - break; - case 's': /* qemu_st data 32-bit constraint */ - ct->regs = 0xffffffff; - goto reserve_helpers; - case 'S': /* qemu_st data 64-bit constraint */ - ct->regs = ALL_64; - goto reserve_helpers; - case 'I': - ct->ct |= TCG_CT_CONST_S11; - break; - case 'J': - ct->ct |= TCG_CT_CONST_S13; - break; - case 'Z': - ct->ct |= TCG_CT_CONST_ZERO; - break; - default: - return NULL; - } - return ct_str; -} - /* test if a constant matches the constraint */ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, const TCGArgConstraint *arg_ct)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/sparc/tcg-target-con-str.h | 22 +++++++++++++++++ tcg/sparc/tcg-target.h | 5 +--- tcg/sparc/tcg-target.c.inc | 45 +++++----------------------------- 3 files changed, 29 insertions(+), 43 deletions(-) create mode 100644 tcg/sparc/tcg-target-con-str.h -- 2.25.1