From patchwork Thu Jan 21 17:17:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 367849 Delivered-To: patch@linaro.org Received: by 2002:a02:a60d:0:0:0:0:0 with SMTP id c13csp761007jam; Thu, 21 Jan 2021 09:19:23 -0800 (PST) X-Google-Smtp-Source: ABdhPJy4WocdddONE8z1GgBZdKmmkfMgNgrU9ik/7vOf2ib2o//Ze/eX7XZtPN92ne9Z5+qYsb6R X-Received: by 2002:a05:6402:4242:: with SMTP id g2mr126350edb.103.1611249563609; Thu, 21 Jan 2021 09:19:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1611249563; cv=none; d=google.com; s=arc-20160816; b=QkYDJmJTlwyMJnDX2rA+E768LNv1Egovh0hSiCkj6TiO9dY/kXy5+fUoA1SyhxNbUU 6qnNUO30TaEoGZhFx9ZHIsSn627XcosGJ881f36HXCo78l28NNMcybZb7Zd48RBB4yqj XMVv767s2mJp1E2Db3OgfOl0F4osycldtnNVPxFV6S+kchSbzgKe7fCf+H9MxPZ7pGMH x3sGmFZKQz5kP0nsxnfC8NZ/MFRwfwYQGXoOBmdwfsG75sYUdMs2gXsglzOyye1HcVzC L2HQPeQqv3U5+h4MuRxXYGcximnnpPgYtWD8IZo0fo4ql/idJPkPQ/iSSkXiKBB1lJOc IG0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GpoBrMIPXNsIIYHDUabOz2zTd7DblvaRcGxnZSl4WVc=; b=u8j5JEb/XZf0IXqR3lGAPHdQNpYkSKccfUjMJ4iFkuFPgwt4vlR6fJB0OEa9xZVrEP XS077yGPxvj4Vbcjj/zBTOU7ffwn8oVTWiiKbY4sci3cBFOdjeUAYSq5LMmi7GjAYhVH /HuKEIeplbBtLeI30lbkVrx9udeYyUDS1983EaEmoJsSbnPQ1jBwjc9HWxLmyVLm3w3W AVHUJfIVwIOYGHSlasRA+8PyjUEXuSI26n49cozHypk5RiCGA8MrCSlsMq3UOAfHEQRG qpvT7/aez13LpQ4QKkr8nNy7JbyxROSKVYq38HxQZ6XH3ogJCLi627CG9WpjEXsPVoDT HVaQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=dNwaKnGo; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id u18si1966760ejh.429.2021.01.21.09.19.23; Thu, 21 Jan 2021 09:19:23 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=dNwaKnGo; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388728AbhAURTS (ORCPT + 6 others); Thu, 21 Jan 2021 12:19:18 -0500 Received: from mail.kernel.org ([198.145.29.99]:43098 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388817AbhAURSm (ORCPT ); Thu, 21 Jan 2021 12:18:42 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id B36F223A59; Thu, 21 Jan 2021 17:17:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1611249481; bh=5DDiBkNKQOZV+EMpAb4nVUfs3FoM3oO0Axt0caXbGYg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dNwaKnGosJrZ8B91GJZGuRoF2rKeYoaxBX6hBtCxzHnBCSbx/OfvuYzKVCoS1Lssd v/Om/e0VogWQL/m4/cW3blwHOB6QgvLMZiujEMvjc6DjkE6EeqzXQdJ4yVMDG7vzho gqBEfBXhK57RrzMe4tlOUjcZdmPV2dLOw+pxyp634tl5p6D3k+12LUpbLcNy9bjP0q cx6gj8IIZ++UYxlWpkHm46Hr92kafU2AN875RJZSkAqA6UeMwv7Zk19nbVfQAFcoJX RgAnC8e/eK/EmcbuNcodhlK51QuR2ZdxiVPngoOcEli2LjwKGuDpi2d0C27hIZm7LI NLeslvYocFtBg== From: Vinod Koul To: Linus Walleij Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Rob Herring , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 1/2] dt-bindings: pinctrl: qcom: Add SM8350 pinctrl bindings Date: Thu, 21 Jan 2021 22:47:46 +0530 Message-Id: <20210121171747.3161543-2-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210121171747.3161543-1-vkoul@kernel.org> References: <20210121171747.3161543-1-vkoul@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree binding Documentation details for Qualcomm SM8350 pinctrl driver. Signed-off-by: Vinod Koul --- .../bindings/pinctrl/qcom,sm8350-pinctrl.yaml | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml -- 2.26.2 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml new file mode 100644 index 000000000000..706bc79db60b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM8350 TLMM block + +maintainers: + - Vinod Koul + +description: | + This binding describes the Top Level Mode Multiplexer (TLMM) block found + in the SM8350 platform. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm8350-tlmm + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + '#interrupt-cells': true + gpio-controller: true + gpio-reserved-ranges: true + '#gpio-cells': true + gpio-ranges: true + wakeup-parent: true + +required: + - compatible + - reg + +additionalProperties: false + +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-sm8350-tlmm-state" + - patternProperties: + ".*": + $ref: "#/$defs/qcom-sm8350-tlmm-state" + +'$defs': + qcom-sm8350-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-3])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, + cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, + ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, + gpio, ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, + mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, + mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, + mi2s1_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, + mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, + mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, + mss_grfc7, mss_grfc8, mss_grfc9, nav_gpio, pa_indicator, + pcie0_clkreqn, pcie1_clkreqn, phase_flag, pll_bist, pll_clk, + pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, + qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request, + qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0, + qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, + qup11, qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, + qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, + qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, + sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, + tgu_ch3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, + uim0_present, uim0_reset, uim1_clk, uim1_data, uim1_present, + uim1_reset, usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ] + + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + phandle: true + + required: + - pins + - function + + additionalProperties: false + +examples: + - | + #include + pinctrl@f100000 { + compatible = "qcom,sm8350-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 203>; + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx { + pins = "gpio18"; + function = "qup3"; + bias-pull-up; + }; + + tx { + pins = "gpio19"; + function = "qup3"; + bias-disable; + }; + }; + }; +...