| Message ID | 20210121061804.26423-2-irui.wang@mediatek.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/3] dt-bindings: media: mtk-vcodec: Separating mtk vcodec encoder node | expand |
On Thu, 2021-01-21 at 14:18 +0800, Irui Wang wrote: > There are two separate hardware encoder blocks inside MT8173. > Split the current mtk-vcodec-enc node to match the hardware architecture. > > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > Signed-off-by: Maoguang Meng <maoguang.meng@mediatek.com> > Signed-off-by: Irui Wang <irui.wang@mediatek.com> > Acked-by: Tiffany Lin <tiffany.lin@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 60 ++++++++++++------------ > 1 file changed, 31 insertions(+), 29 deletions(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > index 7fa870e4386a..d667b296c512 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > @@ -1459,13 +1459,10 @@ > }; > > vcodec_enc: vcodec@18002000 { > - compatible = "mediatek,mt8173-vcodec-enc"; > - reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ > - <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ > - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, > - <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; > - mediatek,larb = <&larb3>, > - <&larb5>; > + compatible = "mediatek,mt8173-vcodec-avc-enc"; > + reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */ > + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; > + mediatek,larb = <&larb3>; > iommus = <&iommu M4U_PORT_VENC_RCPU>, > <&iommu M4U_PORT_VENC_REC>, > <&iommu M4U_PORT_VENC_BSDMA>, > @@ -1476,29 +1473,12 @@ > <&iommu M4U_PORT_VENC_REF_LUMA>, > <&iommu M4U_PORT_VENC_REF_CHROMA>, > <&iommu M4U_PORT_VENC_NBM_RDMA>, > - <&iommu M4U_PORT_VENC_NBM_WDMA>, > - <&iommu M4U_PORT_VENC_RCPU_SET2>, > - <&iommu M4U_PORT_VENC_REC_FRM_SET2>, > - <&iommu M4U_PORT_VENC_BSDMA_SET2>, > - <&iommu M4U_PORT_VENC_SV_COMA_SET2>, > - <&iommu M4U_PORT_VENC_RD_COMA_SET2>, > - <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, > - <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, > - <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, > - <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; > + <&iommu M4U_PORT_VENC_NBM_WDMA>; > mediatek,vpu = <&vpu>; > - clocks = <&topckgen CLK_TOP_VENCPLL_D2>, > - <&topckgen CLK_TOP_VENC_SEL>, > - <&topckgen CLK_TOP_UNIVPLL1_D2>, > - <&topckgen CLK_TOP_VENC_LT_SEL>; > - clock-names = "venc_sel_src", > - "venc_sel", > - "venc_lt_sel_src", > - "venc_lt_sel"; > - assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, > - <&topckgen CLK_TOP_VENC_LT_SEL>; > - assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>, > - <&topckgen CLK_TOP_VCODECPLL_370P5>; > + clocks = <&topckgen CLK_TOP_VENC_SEL>; > + clock-names = "venc_sel"; > + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; > }; > > jpegdec: jpegdec@18004000 { > @@ -1530,5 +1510,27 @@ > <&vencltsys CLK_VENCLT_CKE0>; > clock-names = "apb", "smi"; > }; > + > + vcodec_enc_lt: vcodec@19002000 { > + compatible = "mediatek,mt8173-vcodec-vp8-enc"; > + reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ > + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; > + iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, > + <&iommu M4U_PORT_VENC_REC_FRM_SET2>, > + <&iommu M4U_PORT_VENC_BSDMA_SET2>, > + <&iommu M4U_PORT_VENC_SV_COMA_SET2>, > + <&iommu M4U_PORT_VENC_RD_COMA_SET2>, > + <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, > + <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, > + <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, > + <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; > + mediatek,larb = <&larb5>; > + mediatek,vpu = <&vpu>; > + clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; > + clock-names = "venc_lt_sel"; > + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; > + assigned-clock-parents = > + <&topckgen CLK_TOP_VCODECPLL_370P5>; > + }; > }; > };
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 7fa870e4386a..d667b296c512 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1459,13 +1459,10 @@ }; vcodec_enc: vcodec@18002000 { - compatible = "mediatek,mt8173-vcodec-enc"; - reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ - <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; - mediatek,larb = <&larb3>, - <&larb5>; + compatible = "mediatek,mt8173-vcodec-avc-enc"; + reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */ + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; + mediatek,larb = <&larb3>; iommus = <&iommu M4U_PORT_VENC_RCPU>, <&iommu M4U_PORT_VENC_REC>, <&iommu M4U_PORT_VENC_BSDMA>, @@ -1476,29 +1473,12 @@ <&iommu M4U_PORT_VENC_REF_LUMA>, <&iommu M4U_PORT_VENC_REF_CHROMA>, <&iommu M4U_PORT_VENC_NBM_RDMA>, - <&iommu M4U_PORT_VENC_NBM_WDMA>, - <&iommu M4U_PORT_VENC_RCPU_SET2>, - <&iommu M4U_PORT_VENC_REC_FRM_SET2>, - <&iommu M4U_PORT_VENC_BSDMA_SET2>, - <&iommu M4U_PORT_VENC_SV_COMA_SET2>, - <&iommu M4U_PORT_VENC_RD_COMA_SET2>, - <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, - <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, - <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, - <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; + <&iommu M4U_PORT_VENC_NBM_WDMA>; mediatek,vpu = <&vpu>; - clocks = <&topckgen CLK_TOP_VENCPLL_D2>, - <&topckgen CLK_TOP_VENC_SEL>, - <&topckgen CLK_TOP_UNIVPLL1_D2>, - <&topckgen CLK_TOP_VENC_LT_SEL>; - clock-names = "venc_sel_src", - "venc_sel", - "venc_lt_sel_src", - "venc_lt_sel"; - assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, - <&topckgen CLK_TOP_VENC_LT_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>, - <&topckgen CLK_TOP_VCODECPLL_370P5>; + clocks = <&topckgen CLK_TOP_VENC_SEL>; + clock-names = "venc_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; }; jpegdec: jpegdec@18004000 { @@ -1530,5 +1510,27 @@ <&vencltsys CLK_VENCLT_CKE0>; clock-names = "apb", "smi"; }; + + vcodec_enc_lt: vcodec@19002000 { + compatible = "mediatek,mt8173-vcodec-vp8-enc"; + reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; + iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, + <&iommu M4U_PORT_VENC_REC_FRM_SET2>, + <&iommu M4U_PORT_VENC_BSDMA_SET2>, + <&iommu M4U_PORT_VENC_SV_COMA_SET2>, + <&iommu M4U_PORT_VENC_RD_COMA_SET2>, + <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, + <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, + <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, + <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; + mediatek,larb = <&larb5>; + mediatek,vpu = <&vpu>; + clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; + clock-names = "venc_lt_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; + assigned-clock-parents = + <&topckgen CLK_TOP_VCODECPLL_370P5>; + }; }; };