| Message ID | 1611488647-12478-9-git-send-email-stefanc@marvell.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | net: mvpp2: Add TX Flow Control support | expand |
On Sun, Jan 24, 2021 at 01:43:57PM +0200, stefanc@marvell.com wrote: > +/* Set Flow Control timer x140 faster than pause quanta to ensure that link > + * partner won't send taffic if port in XOFF mode. Can you explain more why 140 times faster is desirable here? Why 140 times and not, say, 10 times faster? Where does this figure come from, and what is the reasoning? Is there a switch that requires it? Also, spelling "traffic".
On Sun, Jan 24, 2021 at 02:43:30PM +0000, Stefan Chulski wrote: > > > > ---------------------------------------------------------------------- > > On Sun, Jan 24, 2021 at 01:43:57PM +0200, stefanc@marvell.com wrote: > > > +/* Set Flow Control timer x140 faster than pause quanta to ensure > > > +that link > > > + * partner won't send taffic if port in XOFF mode. > > > > Can you explain more why 140 times faster is desirable here? Why 140 times > > and not, say, 10 times faster? Where does this figure come from, and what is > > the reasoning? Is there a switch that requires it? > > I tested with 140. > Actually regarding to spec each quanta should be equal to 512 bit times. > In 10G bit time is 0.1ns. And if the link has been negotiated to 10Mbps? Or is the clock already scaled to the link speed? Andrew
> > > > > > -------------------------------------------------------------------- > > > -- On Sun, Jan 24, 2021 at 01:43:57PM +0200, stefanc@marvell.com > > > wrote: > > > > +/* Set Flow Control timer x140 faster than pause quanta to ensure > > > > +that link > > > > + * partner won't send taffic if port in XOFF mode. > > > > > > Can you explain more why 140 times faster is desirable here? Why 140 > > > times and not, say, 10 times faster? Where does this figure come > > > from, and what is the reasoning? Is there a switch that requires it? > > > > I tested with 140. > > Actually regarding to spec each quanta should be equal to 512 bit times. > > In 10G bit time is 0.1ns. > > And if the link has been negotiated to 10Mbps? Or is the clock already scaled > to the link speed? > > Andrew Currently its static, probably I can add function that reconfigure timer during runtime(based on link speed). Should it be part of this series or add it afterwards? Regards, Stefan.
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h index cac9885..0861c0b 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h @@ -596,6 +596,15 @@ #define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4) #define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11) +/* FCA registers. PPv2.2 and PPv2.3 */ +#define MVPP22_FCA_BASE(port) (0x7600 + (port) * 0x1000) +#define MVPP22_FCA_REG_SIZE 16 +#define MVPP22_FCA_REG_MASK 0xFFFF +#define MVPP22_FCA_CONTROL_REG 0x0 +#define MVPP22_FCA_ENABLE_PERIODIC BIT(11) +#define MVPP22_PERIODIC_COUNTER_LSB_REG (0x110) +#define MVPP22_PERIODIC_COUNTER_MSB_REG (0x114) + /* XPCS registers. PPv2.2 and PPv2.3 */ #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000) #define MVPP22_XPCS_CFG0 0x0 @@ -752,7 +761,9 @@ ((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) /* MSS Flow control */ -#define MSS_SRAM_SIZE 0x800 +#define MSS_SRAM_SIZE 0x800 +#define FC_QUANTA 0xFFFF +#define FC_CLK_DIVIDER 0x140 /* RX buffer constants */ #define MVPP2_SKB_SHINFO_SIZE \ diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c index 7143909..9d69752 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c @@ -1293,6 +1293,49 @@ static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) writel(val, mpcs + MVPP22_MPCS_CLK_RESET); } +static void mvpp22_gop_fca_enable_periodic(struct mvpp2_port *port, bool en) +{ + struct mvpp2 *priv = port->priv; + void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id); + u32 val; + + val = readl(fca + MVPP22_FCA_CONTROL_REG); + val &= ~MVPP22_FCA_ENABLE_PERIODIC; + if (en) + val |= MVPP22_FCA_ENABLE_PERIODIC; + writel(val, fca + MVPP22_FCA_CONTROL_REG); +} + +static void mvpp22_gop_fca_set_timer(struct mvpp2_port *port, u32 timer) +{ + struct mvpp2 *priv = port->priv; + void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id); + u32 lsb, msb; + + lsb = timer & MVPP22_FCA_REG_MASK; + msb = timer >> MVPP22_FCA_REG_SIZE; + + writel(lsb, fca + MVPP22_PERIODIC_COUNTER_LSB_REG); + writel(msb, fca + MVPP22_PERIODIC_COUNTER_MSB_REG); +} + +/* Set Flow Control timer x140 faster than pause quanta to ensure that link + * partner won't send taffic if port in XOFF mode. + */ +static void mvpp22_gop_fca_set_periodic_timer(struct mvpp2_port *port) +{ + u32 timer; + + timer = (port->priv->tclk / (USEC_PER_SEC * FC_CLK_DIVIDER)) + * FC_QUANTA; + + mvpp22_gop_fca_enable_periodic(port, false); + + mvpp22_gop_fca_set_timer(port, timer); + + mvpp22_gop_fca_enable_periodic(port, true); +} + static int mvpp22_gop_init(struct mvpp2_port *port) { struct mvpp2 *priv = port->priv; @@ -1337,6 +1380,8 @@ static int mvpp22_gop_init(struct mvpp2_port *port) val |= GENCONF_SOFT_RESET1_GOP; regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); + mvpp22_gop_fca_set_periodic_timer(port); + unsupported_conf: return 0;