diff mbox series

[v2,4/4] arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS

Message ID 20210209124758.990681-5-dmitry.baryshkov@linaro.org
State Superseded
Headers show
Series arm64: dts: qcom: qrb5165-rb5: use GPIO as SPI0 CS | expand

Commit Message

Dmitry Baryshkov Feb. 9, 2021, 12:47 p.m. UTC 
GENI SPI controller shows several issues if it manages the CS on its own
(see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to
use GPIO for CS")) for the details. Configure SPI0 CS pin as a GPIO.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

---
 arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

-- 
2.30.0
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index dd0ec0676258..4888ac47cc1d 100644
--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
@@ -815,7 +815,7 @@  &pm8150_rtc {
 	status = "okay";
 };
 
-&qup_spi0_cs {
+&qup_spi0_cs_gpio {
 	drive-strength = <6>;
 	bias-disable;
 };
@@ -962,7 +962,8 @@  codec {
 /* CAN */
 &spi0 {
 	status = "okay";
-	pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+	pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs_gpio>;
+	cs-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
 
 	can@0 {
 		compatible = "microchip,mcp2518fd";