diff mbox

[10/13] clocksource: sirf: Disable counter before re-setting it

Message ID 1411950226-21598-10-git-send-email-daniel.lezcano@linaro.org
State Accepted
Commit 28cf35675a66947b20731f6acbc9d5b131930ce3
Headers show

Commit Message

Daniel Lezcano Sept. 29, 2014, 12:23 a.m. UTC 
From: Hao Liu <Hao.Liu@csr.com>

According to HW spec, we have to disable the counter before setting
it, if we don't this, in pressure test, sometimes the timer might
not generate interrupt any more.

And this patch also fixes a typo for register set by changing 0x7
to 0x3. 0x7 is loop mode in HW, but here we are using oneshot 0x3.

Signed-off-by: Hao Liu <Hao.Liu@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
 drivers/clocksource/timer-marco.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
diff mbox

Patch

diff --git a/drivers/clocksource/timer-marco.c b/drivers/clocksource/timer-marco.c
index 330e930..caf7a20 100644
--- a/drivers/clocksource/timer-marco.c
+++ b/drivers/clocksource/timer-marco.c
@@ -63,7 +63,7 @@  static inline void sirfsoc_timer_count_disable(int idx)
 /* enable count and interrupt */
 static inline void sirfsoc_timer_count_enable(int idx)
 {
-	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x7,
+	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3,
 		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
 }
 
@@ -103,6 +103,9 @@  static int sirfsoc_timer_set_next_event(unsigned long delta,
 {
 	int cpu = smp_processor_id();
 
+	/* disable timer first, then modify the related registers */
+	sirfsoc_timer_count_disable(cpu);
+
 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
 		4 * cpu);
 	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +