diff mbox series

[06/13] arm64: dts: qcom: SC7280: Add rpmhcc clock controller node

Message ID 1613114930-1661-7-git-send-email-rnayak@codeaurora.org
State New
Headers show
Series Add binding updates and DT files for SC7280 SoC | expand

Commit Message

Rajendra Nayak Feb. 12, 2021, 7:28 a.m. UTC 
Add rpmhcc clock controller node for SC7280. Also add the 'fixed
clock' nodes which can now be referenced in gcc.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 55 ++++++++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

Comments

Stephen Boyd Feb. 23, 2021, 7:43 a.m. UTC | #1 
Quoting Rajendra Nayak (2021-02-11 23:28:43)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 7848e88..10851e7 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -6,6 +6,7 @@
>   */
>  
>  #include <dt-bindings/clock/qcom,gcc-sc7280.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>  
> @@ -29,6 +30,42 @@
>                         clock-frequency = <32000>;
>                         #clock-cells = <0>;
>                 };
> +
> +               pcie_0_pipe_clk: pcie-0-pipe-clk {
> +                       compatible = "fixed-clock";
> +                       clock-frequency = <1000>;
> +                       #clock-cells = <0>;
> +               };
> +
> +               pcie_1_pipe_clk: pcie-1-pipe-clk {
> +                       compatible = "fixed-clock";
> +                       clock-frequency = <1000>;
> +                       #clock-cells = <0>;
> +               };
> +
> +               ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0-clk {
> +                       compatible = "fixed-clock";
> +                       clock-frequency = <1000>;
> +                       #clock-cells = <0>;
> +               };
> +
> +               ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1-clk {
> +                       compatible = "fixed-clock";
> +                       clock-frequency = <1000>;
> +                       #clock-cells = <0>;
> +               };
> +
> +               ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0-clk {
> +                       compatible = "fixed-clock";
> +                       clock-frequency = <1000>;
> +                       #clock-cells = <0>;
> +               };
> +
> +               usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {
> +                       compatible = "fixed-clock";
> +                       clock-frequency = <1000>;
> +                       #clock-cells = <0>;
> +               };

Shouldn't these come from the phys? Why are they being added here?

>         };
>  
>         reserved_memory: reserved-memory {
> @@ -174,6 +211,17 @@
>                 gcc: clock-controller@100000 {
>                         compatible = "qcom,gcc-sc7280";
>                         reg = <0 0x00100000 0 0x1f0000>;
> +                       clocks = <&rpmhcc RPMH_CXO_CLK>,
> +                                <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
> +                                <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
> +                                <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>,
> +                                <&ufs_phy_tx_symbol_0_clk>,
> +                                <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;

If the phys aren't ready then <0> should work. Unless something goes
wrong?

> +                       clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
> +                                     "pcie_0_pipe_clk", "pcie_1_pipe-clk",
> +                                     "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
> +                                     "ufs_phy_tx_symbol_0_clk",
> +                                     "usb3_phy_wrapper_gcc_usb30_pipe_clk";
>                         #clock-cells = <1>;
>                         #reset-cells = <1>;
>                         #power-domain-cells = <1>;
> @@ -325,6 +373,13 @@
>                                           <SLEEP_TCS   3>,
>                                           <WAKE_TCS    3>,
>                                           <CONTROL_TCS 1>;
> +
> +                       rpmhcc: qcom,rpmhcc {

rpmhcc: clock-controller {

> +                               compatible = "qcom,sc7280-rpmh-clk";
> +                               clocks = <&xo_board>;
> +                               clock-names = "xo";
> +                               #clock-cells = <1>;
> +                       };
>                 };
>         };
>
Taniya Das March 1, 2021, 5:27 p.m. UTC | #2 
Hello Stephen,

Thanks for the review.

On 2/23/2021 1:13 PM, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2021-02-11 23:28:43)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 7848e88..10851e7 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -6,6 +6,7 @@
>>    */
>>   
>>   #include <dt-bindings/clock/qcom,gcc-sc7280.h>
>> +#include <dt-bindings/clock/qcom,rpmh.h>
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>   #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>>   
>> @@ -29,6 +30,42 @@
>>                          clock-frequency = <32000>;
>>                          #clock-cells = <0>;
>>                  };
>> +
>> +               pcie_0_pipe_clk: pcie-0-pipe-clk {
>> +                       compatible = "fixed-clock";
>> +                       clock-frequency = <1000>;
>> +                       #clock-cells = <0>;
>> +               };
>> +
>> +               pcie_1_pipe_clk: pcie-1-pipe-clk {
>> +                       compatible = "fixed-clock";
>> +                       clock-frequency = <1000>;
>> +                       #clock-cells = <0>;
>> +               };
>> +
>> +               ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0-clk {
>> +                       compatible = "fixed-clock";
>> +                       clock-frequency = <1000>;
>> +                       #clock-cells = <0>;
>> +               };
>> +
>> +               ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1-clk {
>> +                       compatible = "fixed-clock";
>> +                       clock-frequency = <1000>;
>> +                       #clock-cells = <0>;
>> +               };
>> +
>> +               ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0-clk {
>> +                       compatible = "fixed-clock";
>> +                       clock-frequency = <1000>;
>> +                       #clock-cells = <0>;
>> +               };
>> +
>> +               usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {
>> +                       compatible = "fixed-clock";
>> +                       clock-frequency = <1000>;
>> +                       #clock-cells = <0>;
>> +               };
> 
> Shouldn't these come from the phys? Why are they being added here?
> 

Once the phys are added, these could be replaced, that was the reason to 
add them.

>>          };
>>   
>>          reserved_memory: reserved-memory {
>> @@ -174,6 +211,17 @@
>>                  gcc: clock-controller@100000 {
>>                          compatible = "qcom,gcc-sc7280";
>>                          reg = <0 0x00100000 0 0x1f0000>;
>> +                       clocks = <&rpmhcc RPMH_CXO_CLK>,
>> +                                <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
>> +                                <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
>> +                                <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>,
>> +                                <&ufs_phy_tx_symbol_0_clk>,
>> +                                <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
> 
> If the phys aren't ready then <0> should work. Unless something goes
> wrong?
>

Nothing would go wrong if we add <0>, but wanted them to be replaced 
once the support is added.


>> +                       clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
>> +                                     "pcie_0_pipe_clk", "pcie_1_pipe-clk",
>> +                                     "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
>> +                                     "ufs_phy_tx_symbol_0_clk",
>> +                                     "usb3_phy_wrapper_gcc_usb30_pipe_clk";
>>                          #clock-cells = <1>;
>>                          #reset-cells = <1>;
>>                          #power-domain-cells = <1>;
>> @@ -325,6 +373,13 @@
>>                                            <SLEEP_TCS   3>,
>>                                            <WAKE_TCS    3>,
>>                                            <CONTROL_TCS 1>;
>> +
>> +                       rpmhcc: qcom,rpmhcc {
> 
> rpmhcc: clock-controller {
> 

Will update in the next patch.

>> +                               compatible = "qcom,sc7280-rpmh-clk";
>> +                               clocks = <&xo_board>;
>> +                               clock-names = "xo";
>> +                               #clock-cells = <1>;
>> +                       };
>>                  };
>>          };
>>
Stephen Boyd March 3, 2021, 8:21 a.m. UTC | #3 
Quoting Taniya Das (2021-03-01 09:27:06)
> On 2/23/2021 1:13 PM, Stephen Boyd wrote:
> > Quoting Rajendra Nayak (2021-02-11 23:28:43)
> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >> +               usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {
> >> +                       compatible = "fixed-clock";
> >> +                       clock-frequency = <1000>;
> >> +                       #clock-cells = <0>;
> >> +               };
> > 
> > Shouldn't these come from the phys? Why are they being added here?
> > 
> 
> Once the phys are added, these could be replaced, that was the reason to 
> add them.
> 
> >>          };
> >>   
> >>          reserved_memory: reserved-memory {
> >> @@ -174,6 +211,17 @@
> >>                  gcc: clock-controller@100000 {
> >>                          compatible = "qcom,gcc-sc7280";
> >>                          reg = <0 0x00100000 0 0x1f0000>;
> >> +                       clocks = <&rpmhcc RPMH_CXO_CLK>,
> >> +                                <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
> >> +                                <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
> >> +                                <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>,
> >> +                                <&ufs_phy_tx_symbol_0_clk>,
> >> +                                <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
> > 
> > If the phys aren't ready then <0> should work. Unless something goes
> > wrong?
> >
> 
> Nothing would go wrong if we add <0>, but wanted them to be replaced 
> once the support is added.

Please use <0> to indicate that it's missing. Otherwise we may never
realize that we should connect it up later.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 7848e88..10851e7 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -6,6 +6,7 @@ 
  */
 
 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
@@ -29,6 +30,42 @@ 
 			clock-frequency = <32000>;
 			#clock-cells = <0>;
 		};
+
+		pcie_0_pipe_clk: pcie-0-pipe-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			#clock-cells = <0>;
+		};
+
+		pcie_1_pipe_clk: pcie-1-pipe-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			#clock-cells = <0>;
+		};
+
+		ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			#clock-cells = <0>;
+		};
+
+		ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			#clock-cells = <0>;
+		};
+
+		ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			#clock-cells = <0>;
+		};
+
+		usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <1000>;
+			#clock-cells = <0>;
+		};
 	};
 
 	reserved_memory: reserved-memory {
@@ -174,6 +211,17 @@ 
 		gcc: clock-controller@100000 {
 			compatible = "qcom,gcc-sc7280";
 			reg = <0 0x00100000 0 0x1f0000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
+				 <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
+				 <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>,
+				 <&ufs_phy_tx_symbol_0_clk>,
+				 <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
+			clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
+				      "pcie_0_pipe_clk", "pcie_1_pipe-clk",
+				      "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
+				      "ufs_phy_tx_symbol_0_clk",
+				      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
@@ -325,6 +373,13 @@ 
 					  <SLEEP_TCS   3>,
 					  <WAKE_TCS    3>,
 					  <CONTROL_TCS 1>;
+
+			rpmhcc: qcom,rpmhcc {
+				compatible = "qcom,sc7280-rpmh-clk";
+				clocks = <&xo_board>;
+				clock-names = "xo";
+				#clock-cells = <1>;
+			};
 		};
 	};