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target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any"

Message ID 1412966807-20844-1-git-send-email-peter.maydell@linaro.org
State Superseded
Headers show

Commit Message

Peter Maydell Oct. 10, 2014, 6:46 p.m. UTC
For the CPU type "any" (only used with linux-user) we were reporting
the L1Ip field as 0b00, which is reserved. Change this field to 0b10
instead, indicating a VIPT icache as the comment describes.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/cpu64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Laurent Desnogues Oct. 11, 2014, 8:51 a.m. UTC | #1
On Fri, Oct 10, 2014 at 8:46 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> For the CPU type "any" (only used with linux-user) we were reporting
> the L1Ip field as 0b00, which is reserved. Change this field to 0b10
> instead, indicating a VIPT icache as the comment describes.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Thanks,

Laurent

> ---
>  target-arm/cpu64.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
> index c30f47e..4807ce1 100644
> --- a/target-arm/cpu64.c
> +++ b/target-arm/cpu64.c
> @@ -151,7 +151,7 @@ static void aarch64_any_initfn(Object *obj)
>      set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
>      set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
>      set_feature(&cpu->env, ARM_FEATURE_CRC);
> -    cpu->ctr = 0x80030003; /* 32 byte I and D cacheline size, VIPT icache */
> +    cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
>      cpu->dcz_blocksize = 7; /*  512 bytes */
>  }
>  #endif
> --
> 1.9.1
>
diff mbox

Patch

diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index c30f47e..4807ce1 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -151,7 +151,7 @@  static void aarch64_any_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
     set_feature(&cpu->env, ARM_FEATURE_CRC);
-    cpu->ctr = 0x80030003; /* 32 byte I and D cacheline size, VIPT icache */
+    cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
     cpu->dcz_blocksize = 7; /*  512 bytes */
 }
 #endif