[01/20] ARM/ARM64: KVM: Nuke Hyp-mode tlbs before enabling MMU

Message ID 1413538344-11920-2-git-send-email-zhuyijun@huawei.com
State New
Headers show

Commit Message

zhuyijun Oct. 17, 2014, 9:32 a.m.
From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>

X-Gene u-boot runs in EL2 mode with MMU enabled hence we might
have stale EL2 tlb enteris when we enable EL2 MMU on each host CPU.

This can happen on any ARM/ARM64 board running bootloader in
Hyp-mode (or EL2-mode) with MMU enabled.

This patch ensures that we flush all Hyp-mode (or EL2-mode) TLBs
on each host CPU before enabling Hyp-mode (or EL2-mode) MMU.

Cc: <stable@vger.kernel.org>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
Signed-off-by: Anup Patel <anup.patel@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
 arch/arm/kvm/init.S       |    4 ++++
 arch/arm64/kvm/hyp-init.S |    4 ++++
 2 files changed, 8 insertions(+), 0 deletions(-)

Comments

Christoffer Dall Oct. 17, 2014, 9:36 a.m. | #1
Hi Zhuyjin,

Why are you cc'ing me patches that are already applied to the kvm/arm tree?

This looks like you're doing some git send-email command and forgot to
suppress the CC.  Please be more careful in the future, as this is
quite confusing to everyone!

-Christoffer

On Fri, Oct 17, 2014 at 11:32 AM, zhuyijun <zhuyijun@huawei.com> wrote:
> From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
>
> X-Gene u-boot runs in EL2 mode with MMU enabled hence we might
> have stale EL2 tlb enteris when we enable EL2 MMU on each host CPU.
>
> This can happen on any ARM/ARM64 board running bootloader in
> Hyp-mode (or EL2-mode) with MMU enabled.
>
> This patch ensures that we flush all Hyp-mode (or EL2-mode) TLBs
> on each host CPU before enabling Hyp-mode (or EL2-mode) MMU.
>
> Cc: <stable@vger.kernel.org>
> Tested-by: Mark Rutland <mark.rutland@arm.com>
> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
> Signed-off-by: Anup Patel <anup.patel@linaro.org>
> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
> ---
>  arch/arm/kvm/init.S       |    4 ++++
>  arch/arm64/kvm/hyp-init.S |    4 ++++
>  2 files changed, 8 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S
> index 1b9844d..ee4f744 100644
> --- a/arch/arm/kvm/init.S
> +++ b/arch/arm/kvm/init.S
> @@ -98,6 +98,10 @@ __do_hyp_init:
>         mrc     p15, 0, r0, c10, c2, 1
>         mcr     p15, 4, r0, c10, c2, 1
>
> +       @ Invalidate the stale TLBs from Bootloader
> +       mcr     p15, 4, r0, c8, c7, 0   @ TLBIALLH
> +       dsb     ish
> +
>         @ Set the HSCTLR to:
>         @  - ARM/THUMB exceptions: Kernel config (Thumb-2 kernel)
>         @  - Endianness: Kernel config
> diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S
> index d968796..c319116 100644
> --- a/arch/arm64/kvm/hyp-init.S
> +++ b/arch/arm64/kvm/hyp-init.S
> @@ -80,6 +80,10 @@ __do_hyp_init:
>         msr     mair_el2, x4
>         isb
>
> +       /* Invalidate the stale TLBs from Bootloader */
> +       tlbi    alle2
> +       dsb     sy
> +
>         mrs     x4, sctlr_el2
>         and     x4, x4, #SCTLR_EL2_EE   // preserve endianness of EL2
>         ldr     x5, =SCTLR_EL2_FLAGS
> --
> 1.7.1
>
>
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zhuyijun Oct. 20, 2014, 12:37 a.m. | #2
On 2014/10/17 17:36, Christoffer Dall wrote:

> Hi Zhuyjin,
> 
> Why are you cc'ing me patches that are already applied to the kvm/arm tree?
> 
> This looks like you're doing some git send-email command and forgot to
> suppress the CC.  Please be more careful in the future, as this is
> quite confusing to everyone!
> 


I'm sorry for giving trouble to all of you!  It will never happen...

> -Christoffer
> 
> On Fri, Oct 17, 2014 at 11:32 AM, zhuyijun <zhuyijun@huawei.com> wrote:
>> From: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
>>
>> X-Gene u-boot runs in EL2 mode with MMU enabled hence we might
>> have stale EL2 tlb enteris when we enable EL2 MMU on each host CPU.
>>
>> This can happen on any ARM/ARM64 board running bootloader in
>> Hyp-mode (or EL2-mode) with MMU enabled.
>>
>> This patch ensures that we flush all Hyp-mode (or EL2-mode) TLBs
>> on each host CPU before enabling Hyp-mode (or EL2-mode) MMU.
>>
>> Cc: <stable@vger.kernel.org>
>> Tested-by: Mark Rutland <mark.rutland@arm.com>
>> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
>> Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
>> Signed-off-by: Anup Patel <anup.patel@linaro.org>
>> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
>> ---
>>  arch/arm/kvm/init.S       |    4 ++++
>>  arch/arm64/kvm/hyp-init.S |    4 ++++
>>  2 files changed, 8 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S
>> index 1b9844d..ee4f744 100644
>> --- a/arch/arm/kvm/init.S
>> +++ b/arch/arm/kvm/init.S
>> @@ -98,6 +98,10 @@ __do_hyp_init:
>>         mrc     p15, 0, r0, c10, c2, 1
>>         mcr     p15, 4, r0, c10, c2, 1
>>
>> +       @ Invalidate the stale TLBs from Bootloader
>> +       mcr     p15, 4, r0, c8, c7, 0   @ TLBIALLH
>> +       dsb     ish
>> +
>>         @ Set the HSCTLR to:
>>         @  - ARM/THUMB exceptions: Kernel config (Thumb-2 kernel)
>>         @  - Endianness: Kernel config
>> diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S
>> index d968796..c319116 100644
>> --- a/arch/arm64/kvm/hyp-init.S
>> +++ b/arch/arm64/kvm/hyp-init.S
>> @@ -80,6 +80,10 @@ __do_hyp_init:
>>         msr     mair_el2, x4
>>         isb
>>
>> +       /* Invalidate the stale TLBs from Bootloader */
>> +       tlbi    alle2
>> +       dsb     sy
>> +
>>         mrs     x4, sctlr_el2
>>         and     x4, x4, #SCTLR_EL2_EE   // preserve endianness of EL2
>>         ldr     x5, =SCTLR_EL2_FLAGS
>> --
>> 1.7.1
>>
>>
> 
> .
> 



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Patch

diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S
index 1b9844d..ee4f744 100644
--- a/arch/arm/kvm/init.S
+++ b/arch/arm/kvm/init.S
@@ -98,6 +98,10 @@  __do_hyp_init:
 	mrc	p15, 0, r0, c10, c2, 1
 	mcr	p15, 4, r0, c10, c2, 1
 
+	@ Invalidate the stale TLBs from Bootloader
+	mcr	p15, 4, r0, c8, c7, 0	@ TLBIALLH
+	dsb	ish
+
 	@ Set the HSCTLR to:
 	@  - ARM/THUMB exceptions: Kernel config (Thumb-2 kernel)
 	@  - Endianness: Kernel config
diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S
index d968796..c319116 100644
--- a/arch/arm64/kvm/hyp-init.S
+++ b/arch/arm64/kvm/hyp-init.S
@@ -80,6 +80,10 @@  __do_hyp_init:
 	msr	mair_el2, x4
 	isb
 
+	/* Invalidate the stale TLBs from Bootloader */
+	tlbi	alle2
+	dsb	sy
+
 	mrs	x4, sctlr_el2
 	and	x4, x4, #SCTLR_EL2_EE	// preserve endianness of EL2
 	ldr	x5, =SCTLR_EL2_FLAGS