diff mbox series

[v1] clk: qcom: clk-rcg2: Add support for duty-cycle for RCG

Message ID 1615401828-6905-1-git-send-email-tdas@codeaurora.org
State Superseded
Headers show
Series [v1] clk: qcom: clk-rcg2: Add support for duty-cycle for RCG | expand

Commit Message

Taniya Das March 10, 2021, 6:43 p.m. UTC
The root clock generators with MND divider has the capability to support
change in duty-cycle by updating the 'D'. Add the clock ops which would
check all the boundary conditions and enable setting the desired duty-cycle
as per the consumer.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
 drivers/clk/qcom/clk-rcg2.c | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the  Linux Foundation.

Comments

kernel test robot March 10, 2021, 9:05 p.m. UTC | #1
Hi Taniya,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on clk/clk-next]
[also build test WARNING on v5.12-rc2 next-20210310]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Taniya-Das/clk-qcom-clk-rcg2-Add-support-for-duty-cycle-for-RCG/20210311-024657
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: powerpc64-randconfig-r035-20210310 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project cd9a69289c7825d54450cb6829fef2c8e0f1963a)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install powerpc64 cross compiling tool for clang build
        # apt-get install binutils-powerpc64-linux-gnu
        # https://github.com/0day-ci/linux/commit/affeb4ce842dbf391537c4e7279ff85e050e1e47
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Taniya-Das/clk-qcom-clk-rcg2-Add-support-for-duty-cycle-for-RCG/20210311-024657
        git checkout affeb4ce842dbf391537c4e7279ff85e050e1e47
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=powerpc64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/clk/qcom/clk-rcg2.c:377:36: warning: variable 'duty_per' is uninitialized when used here [-Wuninitialized]
           d_val = DIV_ROUND_CLOSEST(n_val * duty_per * 2, 100);
                                             ^~~~~~~~
   include/linux/math.h:87:18: note: expanded from macro 'DIV_ROUND_CLOSEST'
           typeof(x) __x = x;                              \
                           ^
   drivers/clk/qcom/clk-rcg2.c:363:64: note: initialize the variable 'duty_per' to silence this warning
           u32 notn_m_val, n_val, m_val, d_val, not2d_val, mask, duty_per;
                                                                         ^
                                                                          = 0
   1 warning generated.


vim +/duty_per +377 drivers/clk/qcom/clk-rcg2.c

   359	
   360	static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
   361	{
   362		struct clk_rcg2 *rcg = to_clk_rcg2(hw);
   363		u32 notn_m_val, n_val, m_val, d_val, not2d_val, mask, duty_per;
   364		int ret;
   365	
   366		if (!rcg->mnd_width)
   367			return 0;
   368	
   369		mask = BIT(rcg->mnd_width) - 1;
   370	
   371		regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &notn_m_val);
   372		regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m_val);
   373	
   374		n_val = (~(notn_m_val) + m_val) & mask;
   375	
   376		/* Calculate 2d value */
 > 377		d_val = DIV_ROUND_CLOSEST(n_val * duty_per * 2, 100);
   378	
   379		 /* Check BIT WIDTHS OF 2d. If D is too big reduce Duty cycle. */
   380		if (d_val > mask)
   381			d_val = mask;
   382	
   383		if ((d_val / 2) > (n_val - m_val))
   384			d_val = (n_val - m_val) * 2;
   385		else if ((d_val / 2) < (m_val / 2))
   386			d_val = m_val;
   387	
   388		not2d_val = ~d_val & mask;
   389	
   390		ret = regmap_update_bits(rcg->clkr.regmap, RCG_D_OFFSET(rcg), mask,
   391					 not2d_val);
   392		if (ret)
   393			return ret;
   394	
   395		return update_config(rcg);
   396	}
   397	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
diff mbox series

Patch

diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 42f13a2..e070f1a 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -357,6 +357,44 @@  static int clk_rcg2_set_floor_rate_and_parent(struct clk_hw *hw,
 	return __clk_rcg2_set_rate(hw, rate, FLOOR);
 }

+static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
+{
+	struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+	u32 notn_m_val, n_val, m_val, d_val, not2d_val, mask, duty_per;
+	int ret;
+
+	if (!rcg->mnd_width)
+		return 0;
+
+	mask = BIT(rcg->mnd_width) - 1;
+
+	regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &notn_m_val);
+	regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m_val);
+
+	n_val = (~(notn_m_val) + m_val) & mask;
+
+	/* Calculate 2d value */
+	d_val = DIV_ROUND_CLOSEST(n_val * duty_per * 2, 100);
+
+	 /* Check BIT WIDTHS OF 2d. If D is too big reduce Duty cycle. */
+	if (d_val > mask)
+		d_val = mask;
+
+	if ((d_val / 2) > (n_val - m_val))
+		d_val = (n_val - m_val) * 2;
+	else if ((d_val / 2) < (m_val / 2))
+		d_val = m_val;
+
+	not2d_val = ~d_val & mask;
+
+	ret = regmap_update_bits(rcg->clkr.regmap, RCG_D_OFFSET(rcg), mask,
+				 not2d_val);
+	if (ret)
+		return ret;
+
+	return update_config(rcg);
+}
+
 const struct clk_ops clk_rcg2_ops = {
 	.is_enabled = clk_rcg2_is_enabled,
 	.get_parent = clk_rcg2_get_parent,
@@ -365,6 +403,7 @@  const struct clk_ops clk_rcg2_ops = {
 	.determine_rate = clk_rcg2_determine_rate,
 	.set_rate = clk_rcg2_set_rate,
 	.set_rate_and_parent = clk_rcg2_set_rate_and_parent,
+	.set_duty_cycle = clk_rcg2_set_duty_cycle,
 };
 EXPORT_SYMBOL_GPL(clk_rcg2_ops);

@@ -376,6 +415,7 @@  const struct clk_ops clk_rcg2_floor_ops = {
 	.determine_rate = clk_rcg2_determine_floor_rate,
 	.set_rate = clk_rcg2_set_floor_rate,
 	.set_rate_and_parent = clk_rcg2_set_floor_rate_and_parent,
+	.set_duty_cycle = clk_rcg2_set_duty_cycle,
 };
 EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);