| Message ID | 1414707132-24588-5-git-send-email-greg.bellows@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 30 October 2014 at 22:12, Greg Bellows <greg.bellows@linaro.org> wrote: > From: Fabian Aggeler <aggelerf@ethz.ch> > > The existing implementation does not support Security Extensions mentioned > in the GICv1 and GICv2 architecture specification. Security Extensions are > not available on all GICs. This property makes it possible to enable Security Extensions. > > It also makes GICD_TYPER/ICDICTR.SecurityExtn RAO for GICs which implement > Security Extensions. > > Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> > > --- > > v1 -> v2 > - Change GICState security extension property from a uint8 type to bool > --- > hw/intc/arm_gic.c | 5 ++++- > hw/intc/arm_gic_common.c | 1 + > include/hw/intc/arm_gic_common.h | 1 + > 3 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c > index ea05f8f..0ee7778 100644 > --- a/hw/intc/arm_gic.c > +++ b/hw/intc/arm_gic.c > @@ -298,7 +298,10 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset) > if (offset == 0) > return s->enabled; > if (offset == 4) > - return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5); > + /* Interrupt Controller Type Register */ > + return ((s->num_irq / 32) - 1) > + | ((NUM_CPU(s) - 1) << 5) > + | (s->security_extn << 10); > if (offset < 0x08) > return 0; > if (offset >= 0x80) { > diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c > index 18b01ba..e35049d 100644 > --- a/hw/intc/arm_gic_common.c > +++ b/hw/intc/arm_gic_common.c > @@ -149,6 +149,7 @@ static Property arm_gic_common_properties[] = { > * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".) > */ > DEFINE_PROP_UINT32("revision", GICState, revision, 1), > + DEFINE_PROP_BOOL("security-extn", GICState, security_extn, 0), Could use a comment describing the property. Also, we should make the name of the property be in line with what we picked for board or CPU level TZ properties. I think that's "secure". Trying to set this property on something that's not a GICv1 or GICv2 should cause an error at realize. > DEFINE_PROP_END_OF_LIST(), > }; > > diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h > index 01c6f24..7825134 100644 > --- a/include/hw/intc/arm_gic_common.h > +++ b/include/hw/intc/arm_gic_common.h > @@ -105,6 +105,7 @@ typedef struct GICState { > MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ > uint32_t num_irq; > uint32_t revision; > + bool security_extn; > int dev_fd; /* kvm device fd if backed by kvm vgic support */ > } GICState; -- PMM
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index ea05f8f..0ee7778 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -298,7 +298,10 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset) if (offset == 0) return s->enabled; if (offset == 4) - return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5); + /* Interrupt Controller Type Register */ + return ((s->num_irq / 32) - 1) + | ((NUM_CPU(s) - 1) << 5) + | (s->security_extn << 10); if (offset < 0x08) return 0; if (offset >= 0x80) { diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 18b01ba..e35049d 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -149,6 +149,7 @@ static Property arm_gic_common_properties[] = { * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".) */ DEFINE_PROP_UINT32("revision", GICState, revision, 1), + DEFINE_PROP_BOOL("security-extn", GICState, security_extn, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index 01c6f24..7825134 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -105,6 +105,7 @@ typedef struct GICState { MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ uint32_t num_irq; uint32_t revision; + bool security_extn; int dev_fd; /* kvm device fd if backed by kvm vgic support */ } GICState;