| Message ID | 1414707132-24588-6-git-send-email-greg.bellows@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 30 October 2014 at 22:12, Greg Bellows <greg.bellows@linaro.org> wrote: > From: Fabian Aggeler <aggelerf@ethz.ch> > > Security Extensions for GICv1 and GICv2 use register banking > to provide transparent access to seperate Secure and Non-secure > copies of GIC configuration registers. This function will later > be replaced by code determining the security state of a read/write > access to a register. > > Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> > --- > hw/intc/arm_gic.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c > index 0ee7778..bee71a1 100644 > --- a/hw/intc/arm_gic.c > +++ b/hw/intc/arm_gic.c > @@ -45,6 +45,13 @@ static inline int gic_get_current_cpu(GICState *s) > return 0; > } > > +/* Security state of a read / write access */ > +static inline bool ns_access(void) > +{ > + /* TODO: use actual security state */ > + return true; > +} We can do this with the transaction attributes patchset now. However this function and its callsites will need adjusting because we need the MemTxAttrs value to answer the question. (Given that the question is just "attrs.secure" we probably don't need the wrapper unless we want to include in this "accesses are always secure if the GIC doesn't implement the security extensions" logic.) -- PMM
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 0ee7778..bee71a1 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -45,6 +45,13 @@ static inline int gic_get_current_cpu(GICState *s) return 0; } +/* Security state of a read / write access */ +static inline bool ns_access(void) +{ + /* TODO: use actual security state */ + return true; +} + /* TODO: Many places that call this routine could be optimized. */ /* Update interrupt status after enabled or pending bits have been changed. */ void gic_update(GICState *s)