| Message ID | 1414707132-24588-11-git-send-email-greg.bellows@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 30 October 2014 at 22:12, Greg Bellows <greg.bellows@linaro.org> wrote: > From: Fabian Aggeler <aggelerf@ethz.ch> > > For GICs with Security Extensions Non-secure reads have a restricted > view on the current running priority. > > Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> > --- > hw/intc/arm_gic.c | 17 ++++++++++++++++- > hw/intc/gic_internal.h | 1 + > 2 files changed, 17 insertions(+), 1 deletion(-) > > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c > index 3761d12..9b021d7 100644 > --- a/hw/intc/arm_gic.c > +++ b/hw/intc/arm_gic.c > @@ -314,6 +314,21 @@ void gic_set_cpu_control(GICState *s, int cpu, uint32_t value) > } > } > > +uint8_t gic_get_running_priority(GICState *s, int cpu) > +{ > + if (s->security_extn && ns_access()) { > + if (s->running_priority[cpu] & 0x80) { > + /* Running priority in upper half, return Non-secure view */ > + return s->running_priority[cpu] << 1; > + } else { > + /* Running priority in lower half, RAZ */ > + return 0; > + } > + } else { > + return s->running_priority[cpu]; > + } > +} > + > void gic_complete_irq(GICState *s, int cpu, int irq) > { > int update = 0; > @@ -849,7 +864,7 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) > case 0x0c: /* Acknowledge */ > return gic_acknowledge_irq(s, cpu); > case 0x14: /* Running Priority */ > - return s->running_priority[cpu]; > + return gic_get_running_priority(s, cpu); > case 0x18: /* Highest Pending Interrupt */ > return s->current_pending[cpu]; > case 0x1c: /* Aliased Binary Point */ > diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h > index e360de6..821ce16 100644 > --- a/hw/intc/gic_internal.h > +++ b/hw/intc/gic_internal.h > @@ -78,6 +78,7 @@ void gic_init_irqs_and_distributor(GICState *s); > void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val); > uint32_t gic_get_cpu_control(GICState *s, int cpu); > void gic_set_cpu_control(GICState *s, int cpu, uint32_t value); > +uint8_t gic_get_running_priority(GICState *s, int cpu); I think this patch should be combined with patch 14 (which deals with the other half of the priority register changes.) -- PMM
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 3761d12..9b021d7 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -314,6 +314,21 @@ void gic_set_cpu_control(GICState *s, int cpu, uint32_t value) } } +uint8_t gic_get_running_priority(GICState *s, int cpu) +{ + if (s->security_extn && ns_access()) { + if (s->running_priority[cpu] & 0x80) { + /* Running priority in upper half, return Non-secure view */ + return s->running_priority[cpu] << 1; + } else { + /* Running priority in lower half, RAZ */ + return 0; + } + } else { + return s->running_priority[cpu]; + } +} + void gic_complete_irq(GICState *s, int cpu, int irq) { int update = 0; @@ -849,7 +864,7 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) case 0x0c: /* Acknowledge */ return gic_acknowledge_irq(s, cpu); case 0x14: /* Running Priority */ - return s->running_priority[cpu]; + return gic_get_running_priority(s, cpu); case 0x18: /* Highest Pending Interrupt */ return s->current_pending[cpu]; case 0x1c: /* Aliased Binary Point */ diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index e360de6..821ce16 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -78,6 +78,7 @@ void gic_init_irqs_and_distributor(GICState *s); void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val); uint32_t gic_get_cpu_control(GICState *s, int cpu); void gic_set_cpu_control(GICState *s, int cpu, uint32_t value); +uint8_t gic_get_running_priority(GICState *s, int cpu); static inline bool gic_test_pending(GICState *s, int irq, int cm)