[02/11] arm: omap5: tps659038: rename regulator defines

Message ID 1415284132-6317-2-git-send-email-balbi@ti.com
State Accepted
Commit c27cd33b8ca807501b173a1503df82184d6b9260
Headers show

Commit Message

Felipe Balbi Nov. 6, 2014, 2:28 p.m.
Those regulators don't have any coupling with
what they supply, so remove the suffixes in order
to not confuse anybody.

Signed-off-by: Felipe Balbi <balbi@ti.com>
---
 arch/arm/cpu/armv7/omap5/hw_data.c      | 10 +++++-----
 arch/arm/include/asm/arch-omap5/clock.h | 10 +++++-----
 2 files changed, 10 insertions(+), 10 deletions(-)

Comments

Tom Rini Nov. 10, 2014, 6:47 p.m. | #1
On Thu, Nov 06, 2014 at 08:28:43AM -0600, Felipe Balbi wrote:

> Those regulators don't have any coupling with
> what they supply, so remove the suffixes in order
> to not confuse anybody.
> 
> Signed-off-by: Felipe Balbi <balbi@ti.com>

Reviewed-by: Tom Rini <trini@ti.com>

Patch

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 0257383..8b4d53a 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -365,31 +365,31 @@  struct vcores_data dra752_volts = {
 	.mpu.value	= VDD_MPU_DRA752,
 	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU_NOM,
 	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.mpu.addr	= TPS659038_REG_ADDR_SMPS12_MPU,
+	.mpu.addr	= TPS659038_REG_ADDR_SMPS12,
 	.mpu.pmic	= &tps659038,
 
 	.eve.value	= VDD_EVE_DRA752,
 	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
 	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.eve.addr	= TPS659038_REG_ADDR_SMPS45_EVE,
+	.eve.addr	= TPS659038_REG_ADDR_SMPS45,
 	.eve.pmic	= &tps659038,
 
 	.gpu.value	= VDD_GPU_DRA752,
 	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU_NOM,
 	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.gpu.addr	= TPS659038_REG_ADDR_SMPS6_GPU,
+	.gpu.addr	= TPS659038_REG_ADDR_SMPS6,
 	.gpu.pmic	= &tps659038,
 
 	.core.value	= VDD_CORE_DRA752,
 	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE_NOM,
 	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
-	.core.addr	= TPS659038_REG_ADDR_SMPS7_CORE,
+	.core.addr	= TPS659038_REG_ADDR_SMPS7,
 	.core.pmic	= &tps659038,
 
 	.iva.value	= VDD_IVA_DRA752,
 	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA_NOM,
 	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.iva.addr	= TPS659038_REG_ADDR_SMPS8_IVA,
+	.iva.addr	= TPS659038_REG_ADDR_SMPS8,
 	.iva.pmic	= &tps659038,
 };
 
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 30d9de2..7eacba2 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -278,11 +278,11 @@ 
 
 /* TPS659038 */
 #define TPS659038_I2C_SLAVE_ADDR		0x58
-#define TPS659038_REG_ADDR_SMPS12_MPU		0x23
-#define TPS659038_REG_ADDR_SMPS45_EVE		0x2B
-#define TPS659038_REG_ADDR_SMPS6_GPU		0x2F
-#define TPS659038_REG_ADDR_SMPS7_CORE		0x33
-#define TPS659038_REG_ADDR_SMPS8_IVA		0x37
+#define TPS659038_REG_ADDR_SMPS12		0x23
+#define TPS659038_REG_ADDR_SMPS45		0x2B
+#define TPS659038_REG_ADDR_SMPS6		0x2F
+#define TPS659038_REG_ADDR_SMPS7		0x33
+#define TPS659038_REG_ADDR_SMPS8		0x37
 
 /* TPS */
 #define TPS62361_I2C_SLAVE_ADDR		0x60