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[86.14.224.72]) by mx.google.com with ESMTPSA id b6sm5965492wiy.22.2014.11.08.07.08.09 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 08 Nov 2014 07:08:09 -0800 (PST) From: Leif Lindholm To: edk2-devel@lists.sourceforge.net Date: Sat, 8 Nov 2014 15:08:28 +0000 Message-Id: <1415459308-13653-1-git-send-email-leif.lindholm@linaro.org> X-Mailer: git-send-email 1.7.10.4 X-Spam-Score: -1.5 (-) X-Spam-Report: Spam Filtering performed by mx.sourceforge.net. See http://spamassassin.org/tag/ for more details. -1.5 SPF_CHECK_PASS SPF reports sender host as permitted sender for sender-domain -0.0 SPF_PASS SPF: sender matches SPF record X-Headers-End: 1Xn7ce-0001d6-Lq Subject: [edk2] [PATCH] Increase more ARM address Pcd entries to 64-bit. X-BeenThere: edk2-devel@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list Reply-To: edk2-devel@lists.sourceforge.net List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.sourceforge.net X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: leif.lindholm@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.169 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Some AArch64 platforms have RAM and flash devices >4GB. Update some additional Pcd entries to 64-bit, and change the corresponding PcdGet32 calls to PcdGet64. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm --- ArmPkg/ArmPkg.dec | 8 ++++---- ArmPlatformPkg/ArmPlatformPkg.dec | 2 +- .../Pei/PeiArmPlatformGlobalVariableLib.c | 6 +++--- ArmPlatformPkg/PlatformPei/PlatformPeiLib.c | 2 +- ArmPlatformPkg/PrePeiCore/MainMPCore.c | 4 ++-- ArmPlatformPkg/PrePeiCore/PrePeiCore.c | 4 ++-- 6 files changed, 13 insertions(+), 13 deletions(-) diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index 2a1947b..e5e7c0a 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -87,17 +87,17 @@ # # ARM Secure Firmware PCDs # - gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015 + gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015 gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016 - gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT32|0x0000002F + gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030 # # ARM Normal (or Non Secure) Firmware PCDs # - gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT32|0x0000002B + gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C - gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D + gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E # diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index 20c3c04..b9f38b6 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -70,7 +70,7 @@ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006 # Stack for CPU Cores in Non Secure Mode - gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT32|0x00000009 + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A diff --git a/ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.c b/ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.c index df3e129..2ffbdbe 100644 --- a/ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.c +++ b/ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.c @@ -34,7 +34,7 @@ ArmPlatformGetGlobalVariable ( // Ensure the Global Variable Size have been initialized ASSERT (VariableOffset < PcdGet32 (PcdPeiGlobalVariableSize)); - GlobalVariableBase = PcdGet32 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize); + GlobalVariableBase = PcdGet64 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize); if (VariableSize == 4) { *(UINT32*)Variable = ReadUnaligned32 ((CONST UINT32*)(GlobalVariableBase + VariableOffset)); @@ -57,7 +57,7 @@ ArmPlatformSetGlobalVariable ( // Ensure the Global Variable Size have been initialized ASSERT (VariableOffset < PcdGet32 (PcdPeiGlobalVariableSize)); - GlobalVariableBase = PcdGet32 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize); + GlobalVariableBase = PcdGet64 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize); if (VariableSize == 4) { WriteUnaligned32 ((UINT32*)(GlobalVariableBase + VariableOffset), *(UINT32*)Variable); @@ -78,7 +78,7 @@ ArmPlatformGetGlobalVariableAddress ( // Ensure the Global Variable Size have been initialized ASSERT (VariableOffset < PcdGet32 (PcdPeiGlobalVariableSize)); - GlobalVariableBase = PcdGet32 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize); + GlobalVariableBase = PcdGet64 (PcdCPUCoresStackBase) + PcdGet32 (PcdCPUCorePrimaryStackSize) - PcdGet32 (PcdPeiGlobalVariableSize); return (VOID*)(GlobalVariableBase + VariableOffset); } diff --git a/ArmPlatformPkg/PlatformPei/PlatformPeiLib.c b/ArmPlatformPkg/PlatformPei/PlatformPeiLib.c index 508b10d..df81286 100755 --- a/ArmPlatformPkg/PlatformPei/PlatformPeiLib.c +++ b/ArmPlatformPkg/PlatformPei/PlatformPeiLib.c @@ -24,7 +24,7 @@ PlatformPeim ( VOID ) { - BuildFvHob (PcdGet32(PcdFvBaseAddress), PcdGet32(PcdFvSize)); + BuildFvHob (PcdGet64(PcdFvBaseAddress), PcdGet32(PcdFvSize)); return EFI_SUCCESS; } diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c index d40594f..a86f739 100644 --- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c +++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c @@ -131,7 +131,7 @@ PrimaryMain ( // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at // the base of the primary core stack PpiListSize = ALIGN_VALUE(PpiListSize, 0x4); - TemporaryRamBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) + PpiListSize; + TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize; TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize; // Make sure the size is 8-byte aligned. Once divided by 2, the size should be 4-byte aligned @@ -144,7 +144,7 @@ PrimaryMain ( // Note also: HOBs (pei temp ram) MUST be above stack // SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF); - SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress); + SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress); SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize); SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack) SecCoreData.TemporaryRamSize = TemporaryRamSize; diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c index 93d7e1c..43ae40d 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c @@ -53,7 +53,7 @@ CreatePpiList ( ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList); // Copy the Common and Platform PPis in Temporrary Memory - ListBase = PcdGet32 (PcdCPUCoresStackBase); + ListBase = PcdGet64 (PcdCPUCoresStackBase); CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable)); CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize); @@ -154,7 +154,7 @@ PrePeiCoreGetGlobalVariableMemory ( { ASSERT (GlobalVariableBase != NULL); - *GlobalVariableBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) + + *GlobalVariableBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - (UINTN)PcdGet32 (PcdPeiGlobalVariableSize);