diff mbox series

[12/26] imx8mp_evk: Increase VDD_ARM to 0.95v Overdrive voltage

Message ID 20210319075718.14181-13-peng.fan@oss.nxp.com
State New
Headers show
Series imx: update for i.MX8M | expand

Commit Message

Peng Fan (OSS) March 19, 2021, 7:57 a.m. UTC 
From: Peng Fan <peng.fan@nxp.com>


There is a frequency/timing limitation for SOC and ARM, if SOC is OD
voltage/OD freq, then ARM can't run at ND voltage/1.2Ghz, it may have
timing risk from SOC to ARM.

Current VDD_SOC is set to 0.95v OD voltage in SPL, and kernel will
increase bus clocks to OD frequency before it increases ARM voltage.
So to conform to the limitation, we'd better increases VDD_ARM to OD
voltage in SPL.

Signed-off-by: Ye Li <ye.li@nxp.com>

Signed-off-by: Peng Fan <peng.fan@nxp.com>

---
 board/freescale/imx8mp_evk/spl.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

-- 
2.30.0
diff mbox series

Patch

diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c
index ef14cfc227..6ccf5ac8fa 100644
--- a/board/freescale/imx8mp_evk/spl.c
+++ b/board/freescale/imx8mp_evk/spl.c
@@ -35,6 +35,16 @@  void spl_dram_init(void)
 
 void spl_board_init(void)
 {
+	/*
+	 * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
+	 * not allow to change it. Should set the clock after PMIC
+	 * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
+	 * set by ROM for ND VDD_SOC
+	 */
+	clock_enable(CCGR_GIC, 0);
+	clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
+	clock_enable(CCGR_GIC, 1);
+
 	puts("Normal Boot\n");
 }
 
@@ -84,6 +94,10 @@  int power_init_board(void)
 	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
 	pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
 
+	/* Kernel uses OD/OD freq for SOC */
+	/* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
+	pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
+
 	/* set WDOG_B_CFG to cold reset */
 	pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);