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[209.132.180.67]) by mx.google.com with ESMTP id ms8si6258344pdb.144.2014.11.11.03.33.11 for ; Tue, 11 Nov 2014 03:33:11 -0800 (PST) Received-SPF: none (google.com: stable-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753216AbaKKLdI (ORCPT + 1 other); Tue, 11 Nov 2014 06:33:08 -0500 Received: from szxga01-in.huawei.com ([119.145.14.64]:2645 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752985AbaKKLdA (ORCPT ); Tue, 11 Nov 2014 06:33:00 -0500 Received: from 172.24.2.119 (EHLO szxeml406-hub.china.huawei.com) ([172.24.2.119]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CEG64706; Tue, 11 Nov 2014 19:32:56 +0800 (CST) Received: from linux-2wy1.site (10.107.197.185) by szxeml406-hub.china.huawei.com (10.82.67.93) with Microsoft SMTP Server id 14.3.158.1; Tue, 11 Nov 2014 19:32:45 +0800 From: Hou Pengyang To: , CC: Subject: [PATCH 05/12] ARM: lpae: fix definition of PTE_HWTABLE_PTRS Date: Tue, 11 Nov 2014 11:31:32 +0000 Message-ID: <1415705499-197612-6-git-send-email-houpengyang@huawei.com> X-Mailer: git-send-email 1.8.3.4 In-Reply-To: <1415705499-197612-1-git-send-email-houpengyang@huawei.com> References: <1415705499-197612-1-git-send-email-houpengyang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.107.197.185] X-CFilter-Loop: Reflected Sender: stable-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: stable@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.45 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Will Deacon commit e38a517578d6c0f764b0d0f6e26dcdf9f70c69d7 upstream. For 2-level page tables, PTE_HWTABLE_PTRS describes the offset between Linux PTEs and hardware PTEs. On LPAE, there is no distinction (since we have 64-bit descriptors with plenty of space) so PTE_HWTABLE_PTRS should be 0. Unfortunately, it is wrongly defined as PTRS_PER_PTE, meaning that current pte table flushing is off by a page. Luckily, all current LPAE implementations are SMP, so the hardware walker can snoop L1. This patch fixes the broken definition. Acked-by: Catalin Marinas Signed-off-by: Will Deacon --- arch/arm/include/asm/pgtable-3level.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h index 9445512..6d7c532 100644 --- a/arch/arm/include/asm/pgtable-3level.h +++ b/arch/arm/include/asm/pgtable-3level.h @@ -33,7 +33,7 @@ #define PTRS_PER_PMD 512 #define PTRS_PER_PGD 4 -#define PTE_HWTABLE_PTRS (PTRS_PER_PTE) +#define PTE_HWTABLE_PTRS (0) #define PTE_HWTABLE_OFF (0) #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64))