| Message ID | 20210323144008.166248-1-paul@crapouillou.net |
|---|---|
| State | Accepted |
| Commit | 60a6b73dd821e98fe958b2a83393ccd724b306b1 |
| Headers | show |
| Series | drm/ingenic: Fix pixclock rate for 24-bit serial panels | expand |
Hi, Can I have an ACK for this patch? Then I can apply it to drm-misc-next-fixes. Cheers, -Paul Le mar. 23 mars 2021 à 14:40, Paul Cercueil <paul@crapouillou.net> a écrit : > When using a 24-bit panel on a 8-bit serial bus, the pixel clock > requested by the panel has to be multiplied by 3, since the subpixels > are shifted sequentially. > > The code (in ingenic_drm_encoder_atomic_check) already computed > crtc_state->adjusted_mode->crtc_clock accordingly, but clk_set_rate() > used crtc_state->adjusted_mode->clock instead. > > Fixes: 28ab7d35b6e0 ("drm/ingenic: Properly compute timings when > using a 3x8-bit panel") > Cc: stable@vger.kernel.org # v5.10 > Signed-off-by: Paul Cercueil <paul@crapouillou.net> > --- > drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > index d60e1eefc9d1..cba68bf52ec5 100644 > --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > @@ -342,7 +342,7 @@ static void ingenic_drm_crtc_atomic_flush(struct > drm_crtc *crtc, > if (priv->update_clk_rate) { > mutex_lock(&priv->clk_mutex); > clk_set_rate(priv->pix_clk, > - crtc_state->adjusted_mode.clock * 1000); > + crtc_state->adjusted_mode.crtc_clock * 1000); > priv->update_clk_rate = false; > mutex_unlock(&priv->clk_mutex); > } > -- > 2.30.2 >
> Am 12.04.2021 um 16:34 schrieb Paul Cercueil <paul@crapouillou.net>: > > Hi, > > Can I have an ACK for this patch? > > Then I can apply it to drm-misc-next-fixes. > > Cheers, > -Paul > > > Le mar. 23 mars 2021 à 14:40, Paul Cercueil <paul@crapouillou.net> a écrit : >> When using a 24-bit panel on a 8-bit serial bus, the pixel clock >> requested by the panel has to be multiplied by 3, since the subpixels >> are shifted sequentially. >> The code (in ingenic_drm_encoder_atomic_check) already computed >> crtc_state->adjusted_mode->crtc_clock accordingly, but clk_set_rate() >> used crtc_state->adjusted_mode->clock instead. >> Fixes: 28ab7d35b6e0 ("drm/ingenic: Properly compute timings when using a 3x8-bit panel") >> Cc: stable@vger.kernel.org # v5.10 Tested-by: H. Nikolaus Schaller <hns@goldelico.com> # CI20/jz4780 (HDMI) and Alpha400/jz4730 (LCD) >> Signed-off-by: Paul Cercueil <paul@crapouillou.net> >> --- >> drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> index d60e1eefc9d1..cba68bf52ec5 100644 >> --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> @@ -342,7 +342,7 @@ static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc, >> if (priv->update_clk_rate) { >> mutex_lock(&priv->clk_mutex); >> clk_set_rate(priv->pix_clk, >> - crtc_state->adjusted_mode.clock * 1000); >> + crtc_state->adjusted_mode.crtc_clock * 1000); >> priv->update_clk_rate = false; >> mutex_unlock(&priv->clk_mutex); >> } >> -- >> 2.30.2 > >
Hi, Almost two months later, Le mar., mars 23 2021 at 14:40:08 +0000, Paul Cercueil <paul@crapouillou.net> a écrit : > When using a 24-bit panel on a 8-bit serial bus, the pixel clock > requested by the panel has to be multiplied by 3, since the subpixels > are shifted sequentially. > > The code (in ingenic_drm_encoder_atomic_check) already computed > crtc_state->adjusted_mode->crtc_clock accordingly, but clk_set_rate() > used crtc_state->adjusted_mode->clock instead. > > Fixes: 28ab7d35b6e0 ("drm/ingenic: Properly compute timings when > using a 3x8-bit panel") > Cc: stable@vger.kernel.org # v5.10 > Signed-off-by: Paul Cercueil <paul@crapouillou.net> Can I get an ACK for my patch? Thanks! -Paul > --- > drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > index d60e1eefc9d1..cba68bf52ec5 100644 > --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > @@ -342,7 +342,7 @@ static void ingenic_drm_crtc_atomic_flush(struct > drm_crtc *crtc, > if (priv->update_clk_rate) { > mutex_lock(&priv->clk_mutex); > clk_set_rate(priv->pix_clk, > - crtc_state->adjusted_mode.clock * 1000); > + crtc_state->adjusted_mode.crtc_clock * 1000); > priv->update_clk_rate = false; > mutex_unlock(&priv->clk_mutex); > } > -- > 2.30.2 >
On Thu, May 13, 2021 at 01:29:30PM +0100, Paul Cercueil wrote: > Hi, > > Almost two months later, Since you're committer it's expected that you go actively out to look for review or trade with someone else who has some patches that need a quick look. It will not happen automatically, this is on you. Also generally after 2 weeks the patch is lost and you need to ping it. -Daniel > > > Le mar., mars 23 2021 at 14:40:08 +0000, Paul Cercueil > <paul@crapouillou.net> a écrit : > > When using a 24-bit panel on a 8-bit serial bus, the pixel clock > > requested by the panel has to be multiplied by 3, since the subpixels > > are shifted sequentially. > > > > The code (in ingenic_drm_encoder_atomic_check) already computed > > crtc_state->adjusted_mode->crtc_clock accordingly, but clk_set_rate() > > used crtc_state->adjusted_mode->clock instead. > > > > Fixes: 28ab7d35b6e0 ("drm/ingenic: Properly compute timings when using a > > 3x8-bit panel") > > Cc: stable@vger.kernel.org # v5.10 > > Signed-off-by: Paul Cercueil <paul@crapouillou.net> > > Can I get an ACK for my patch? > > Thanks! > -Paul > > > --- > > drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > > b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > > index d60e1eefc9d1..cba68bf52ec5 100644 > > --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > > +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c > > @@ -342,7 +342,7 @@ static void ingenic_drm_crtc_atomic_flush(struct > > drm_crtc *crtc, > > if (priv->update_clk_rate) { > > mutex_lock(&priv->clk_mutex); > > clk_set_rate(priv->pix_clk, > > - crtc_state->adjusted_mode.clock * 1000); > > + crtc_state->adjusted_mode.crtc_clock * 1000); > > priv->update_clk_rate = false; > > mutex_unlock(&priv->clk_mutex); > > } > > -- > > 2.30.2 > > > > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
Hi Daniel, Le lun., mai 17 2021 at 15:15:59 +0200, Daniel Vetter <daniel@ffwll.ch> a écrit : > On Thu, May 13, 2021 at 01:29:30PM +0100, Paul Cercueil wrote: >> Hi, >> >> Almost two months later, > > Since you're committer it's expected that you go actively out to look > for > review or trade with someone else who has some patches that need a > quick > look. It will not happen automatically, this is on you. I maintain all drivers, platform code and DTS for Ingenic SoCs so I do my part, just not in this subsystem. > Also generally after 2 weeks the patch is lost and you need to ping > it. OK. Then I guess I'll just include this one in a future patchset. > -Daniel Cheers, -Paul >> >> >> Le mar., mars 23 2021 at 14:40:08 +0000, Paul Cercueil >> <paul@crapouillou.net> a écrit : >> > When using a 24-bit panel on a 8-bit serial bus, the pixel clock >> > requested by the panel has to be multiplied by 3, since the >> subpixels >> > are shifted sequentially. >> > >> > The code (in ingenic_drm_encoder_atomic_check) already computed >> > crtc_state->adjusted_mode->crtc_clock accordingly, but >> clk_set_rate() >> > used crtc_state->adjusted_mode->clock instead. >> > >> > Fixes: 28ab7d35b6e0 ("drm/ingenic: Properly compute timings when >> using a >> > 3x8-bit panel") >> > Cc: stable@vger.kernel.org # v5.10 >> > Signed-off-by: Paul Cercueil <paul@crapouillou.net> >> >> Can I get an ACK for my patch? >> >> Thanks! >> -Paul >> >> > --- >> > drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 2 +- >> > 1 file changed, 1 insertion(+), 1 deletion(-) >> > >> > diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> > b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> > index d60e1eefc9d1..cba68bf52ec5 100644 >> > --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> > +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c >> > @@ -342,7 +342,7 @@ static void >> ingenic_drm_crtc_atomic_flush(struct >> > drm_crtc *crtc, >> > if (priv->update_clk_rate) { >> > mutex_lock(&priv->clk_mutex); >> > clk_set_rate(priv->pix_clk, >> > - crtc_state->adjusted_mode.clock * 1000); >> > + crtc_state->adjusted_mode.crtc_clock * 1000); >> > priv->update_clk_rate = false; >> > mutex_unlock(&priv->clk_mutex); >> > } >> > -- >> > 2.30.2 >> > >> >> > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c index d60e1eefc9d1..cba68bf52ec5 100644 --- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c +++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c @@ -342,7 +342,7 @@ static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc, if (priv->update_clk_rate) { mutex_lock(&priv->clk_mutex); clk_set_rate(priv->pix_clk, - crtc_state->adjusted_mode.clock * 1000); + crtc_state->adjusted_mode.crtc_clock * 1000); priv->update_clk_rate = false; mutex_unlock(&priv->clk_mutex); }
When using a 24-bit panel on a 8-bit serial bus, the pixel clock requested by the panel has to be multiplied by 3, since the subpixels are shifted sequentially. The code (in ingenic_drm_encoder_atomic_check) already computed crtc_state->adjusted_mode->crtc_clock accordingly, but clk_set_rate() used crtc_state->adjusted_mode->clock instead. Fixes: 28ab7d35b6e0 ("drm/ingenic: Properly compute timings when using a 3x8-bit panel") Cc: stable@vger.kernel.org # v5.10 Signed-off-by: Paul Cercueil <paul@crapouillou.net> --- drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)