Message ID | 20210327110305.3289784-16-dmitry.baryshkov@linaro.org |
---|---|
State | New |
Headers | show |
Series | drm/msm/dsi: refactor MSM DSI PHY/PLL drivers | expand |
On 2021-03-27 04:02, Dmitry Baryshkov wrote: > These drivers do not use vco_delay variable, so drop it from all of > them. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 3 --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 ---- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 3 --- > 3 files changed, 10 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > index e0df12a841b2..bfb96d87d1d7 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > @@ -99,7 +99,6 @@ struct dsi_pll_10nm { > /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */ > spinlock_t postdiv_lock; > > - int vco_delay; > struct dsi_pll_config pll_configuration; > struct dsi_pll_regs reg_setup; > > @@ -771,8 +770,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy > *phy) > pll = &pll_10nm->base; > pll->cfg = phy->cfg; > > - pll_10nm->vco_delay = 1; > - > ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws); > if (ret) { > DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > index 7fe7c8348b42..434d02ffa7fe 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > @@ -122,8 +122,6 @@ struct dsi_pll_14nm { > void __iomem *phy_cmn_mmio; > void __iomem *mmio; > > - int vco_delay; > - > struct dsi_pll_input in; > struct dsi_pll_output out; > > @@ -1012,8 +1010,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy > *phy) > pll = &pll_14nm->base; > pll->cfg = phy->cfg; > > - pll_14nm->vco_delay = 1; > - > ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws); > if (ret) { > DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > index e6c8040e1bd3..f760904efac9 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > @@ -99,7 +99,6 @@ struct dsi_pll_7nm { > /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */ > spinlock_t postdiv_lock; > > - int vco_delay; > struct dsi_pll_config pll_configuration; > struct dsi_pll_regs reg_setup; > > @@ -796,8 +795,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy > *phy) > pll = &pll_7nm->base; > pll->cfg = phy->cfg; > > - pll_7nm->vco_delay = 1; > - > ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws); > if (ret) { > DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index e0df12a841b2..bfb96d87d1d7 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -99,7 +99,6 @@ struct dsi_pll_10nm { /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */ spinlock_t postdiv_lock; - int vco_delay; struct dsi_pll_config pll_configuration; struct dsi_pll_regs reg_setup; @@ -771,8 +770,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) pll = &pll_10nm->base; pll->cfg = phy->cfg; - pll_10nm->vco_delay = 1; - ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 7fe7c8348b42..434d02ffa7fe 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -122,8 +122,6 @@ struct dsi_pll_14nm { void __iomem *phy_cmn_mmio; void __iomem *mmio; - int vco_delay; - struct dsi_pll_input in; struct dsi_pll_output out; @@ -1012,8 +1010,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) pll = &pll_14nm->base; pll->cfg = phy->cfg; - pll_14nm->vco_delay = 1; - ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index e6c8040e1bd3..f760904efac9 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -99,7 +99,6 @@ struct dsi_pll_7nm { /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */ spinlock_t postdiv_lock; - int vco_delay; struct dsi_pll_config pll_configuration; struct dsi_pll_regs reg_setup; @@ -796,8 +795,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) pll = &pll_7nm->base; pll->cfg = phy->cfg; - pll_7nm->vco_delay = 1; - ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);
These drivers do not use vco_delay variable, so drop it from all of them. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 3 --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 ---- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 3 --- 3 files changed, 10 deletions(-) -- 2.30.2