| Message ID | 1617172405-12962-8-git-send-email-victor.liu@nxp.com |
|---|---|
| State | Accepted |
| Commit | 95b9cd1f754793cc8f328e7d30f79c4e7de29fbf |
| Headers | show |
| Series | None | expand |
On Wed, 2021-03-31 at 08:40 -0500, Rob Herring wrote: > On Wed, 31 Mar 2021 14:33:18 +0800, Liu Ying wrote: > > This patch adds bindings for i.MX8qm/qxp Control and Status Registers module. > > > > Reviewed-by: Rob Herring <robh@kernel.org> > > Signed-off-by: Liu Ying <victor.liu@nxp.com> > > --- > > v6->v7: > > * Add Rob's R-b tag. > > > > v5->v6: > > * Drop 'select' schema. (Rob) > > > > v4->v5: > > * Newly introduced in v5. (Rob) > > > > .../devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml | 192 +++++++++++++++++++++ > > 1 file changed, 192 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml > > > > My bot found errors running 'make dt_binding_check' on your patch: > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.example.dt.yaml:0:0: /example-0/syscon@56221000/pxl2dpi: failed to match any schema with compatible: ['fsl,imx8qxp-pxl2dpi'] > Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.example.dt.yaml:0:0: /example-0/syscon@56221000/ldb: failed to match any schema with compatible: ['fsl,imx8qxp-ldb'] > Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.example.dt.yaml:0:0: /example-0/phy@56228300: failed to match any schema with compatible: ['fsl,imx8qxp-mipi-dphy'] > Sorry for the errors. But, my patch passes 'make dt_binding_check' locally upon v5.12-rc1-dontuse at least. My yamllint and dt-schema are up to date. Does your bot _additionally_ check all compatibles in example? I guess I missed something? Regards, Liu Ying > See https://patchwork.ozlabs.org/patch/1460356 > > This check can fail if there are any dependencies. The base for a patch > series is generally the most recent rc1. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit. >
On Thu, Apr 1, 2021 at 4:18 AM Liu Ying <victor.liu@nxp.com> wrote: > > On Wed, 2021-03-31 at 08:40 -0500, Rob Herring wrote: > > On Wed, 31 Mar 2021 14:33:18 +0800, Liu Ying wrote: > > > This patch adds bindings for i.MX8qm/qxp Control and Status Registers module. > > > > > > Reviewed-by: Rob Herring <robh@kernel.org> > > > Signed-off-by: Liu Ying <victor.liu@nxp.com> > > > --- > > > v6->v7: > > > * Add Rob's R-b tag. > > > > > > v5->v6: > > > * Drop 'select' schema. (Rob) > > > > > > v4->v5: > > > * Newly introduced in v5. (Rob) > > > > > > .../devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml | 192 +++++++++++++++++++++ > > > 1 file changed, 192 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml > > > > > > > My bot found errors running 'make dt_binding_check' on your patch: > > > > yamllint warnings/errors: > > > > dtschema/dtc warnings/errors: > > Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.example.dt.yaml:0:0: /example-0/syscon@56221000/pxl2dpi: failed to match any schema with compatible: ['fsl,imx8qxp-pxl2dpi'] > > Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.example.dt.yaml:0:0: /example-0/syscon@56221000/ldb: failed to match any schema with compatible: ['fsl,imx8qxp-ldb'] > > Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.example.dt.yaml:0:0: /example-0/phy@56228300: failed to match any schema with compatible: ['fsl,imx8qxp-mipi-dphy'] > > > > Sorry for the errors. > But, my patch passes 'make dt_binding_check' locally upon > v5.12-rc1-dontuse at least. > My yamllint and dt-schema are up to date. > > Does your bot _additionally_ check all compatibles in example? > I guess I missed something? Yes, it now adds 'DT_CHECKER_FLAGS=-m' which is new and pending in linux-next. It's off by default until we get rid of the ~90 existing cases. Rob
diff --git a/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml b/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml new file mode 100644 index 00000000..f095771 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml @@ -0,0 +1,192 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp Control and Status Registers Module Bindings + +maintainers: + - Liu Ying <victor.liu@nxp.com> + +description: | + As a system controller, the Freescale i.MX8qm/qxp Control and Status + Registers(CSR) module represents a set of miscellaneous registers of a + specific subsystem. It may provide control and/or status report interfaces + to a mix of standalone hardware devices within that subsystem. One typical + use-case is for some other nodes to acquire a reference to the syscon node + by phandle, and the other typical use-case is that the operating system + should consider all subnodes of the CSR module as separate child devices. + +properties: + $nodename: + pattern: "^syscon@[0-9a-f]+$" + + compatible: + items: + - enum: + - fsl,imx8qxp-mipi-lvds-csr + - fsl,imx8qm-lvds-csr + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: ipg + +patternProperties: + "^(ldb|phy|pxl2dpi)$": + type: object + description: The possible child devices of the CSR module. + +required: + - compatible + - reg + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8qxp-mipi-lvds-csr + then: + required: + - pxl2dpi + - ldb + + - if: + properties: + compatible: + contains: + const: fsl,imx8qm-lvds-csr + then: + required: + - phy + - ldb + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8-lpcg.h> + #include <dt-bindings/firmware/imx/rsrc.h> + mipi_lvds_0_csr: syscon@56221000 { + compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd"; + reg = <0x56221000 0x1000>; + clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>; + clock-names = "ipg"; + + mipi_lvds_0_pxl2dpi: pxl2dpi { + compatible = "fsl,imx8qxp-pxl2dpi"; + fsl,sc-resource = <IMX_SC_R_MIPI_0>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>; + }; + + mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>; + }; + + mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>; + }; + }; + }; + }; + + mipi_lvds_0_ldb: ldb { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>; + }; + }; + + port@1 { + reg = <1>; + + /* ... */ + }; + }; + + channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>; + }; + }; + + port@1 { + reg = <1>; + + /* ... */ + }; + }; + }; + }; + + mipi_lvds_0_phy: phy@56228300 { + compatible = "fsl,imx8qxp-mipi-dphy"; + reg = <0x56228300 0x100>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>; + clock-names = "phy_ref"; + #phy-cells = <0>; + fsl,syscon = <&mipi_lvds_0_csr>; + power-domains = <&pd IMX_SC_R_MIPI_0>; + };