diff mbox series

[v1,4/4] arm64: dts: qcom: sdm845: add required clocks on the gcc

Message ID 20210402233944.273275-4-dmitry.baryshkov@linaro.org
State Superseded
Headers show
Series [v1,1/4] dt-bindings: clock: separate SDM845 GCC clock bindings | expand

Commit Message

Dmitry Baryshkov April 2, 2021, 11:39 p.m. UTC
Specify input clocks to the SDM845's Global Clock Controller as required
by the bindings.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

-- 
2.30.2

Comments

Bjorn Andersson April 4, 2021, 2:56 p.m. UTC | #1
On Fri 02 Apr 18:39 CDT 2021, Dmitry Baryshkov wrote:

> Specify input clocks to the SDM845's Global Clock Controller as required

> by the bindings.

> 

> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>


Okay, so that proved me wrong on my suggestion to rely on bi_tcxo always
coming from the DT...

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>


Regards,
Bjorn

> ---

>  arch/arm64/boot/dts/qcom/sdm845.dtsi | 12 ++++++++++++

>  1 file changed, 12 insertions(+)

> 

> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi

> index 454f794af547..86f717d5bfb6 100644

> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi

> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi

> @@ -1061,6 +1061,16 @@ soc: soc@0 {

>  		gcc: clock-controller@100000 {

>  			compatible = "qcom,gcc-sdm845";

>  			reg = <0 0x00100000 0 0x1f0000>;

> +			clocks = <&rpmhcc RPMH_CXO_CLK>,

> +				 <&rpmhcc RPMH_CXO_CLK_A>,

> +				 <&sleep_clk>,

> +				 <&pcie0_lane>,

> +				 <&pcie1_lane>;

> +			clock-names = "bi_tcxo",

> +				      "bi_tcxo_ao",

> +				      "sleep_clk",

> +				      "pcie_0_pipe_clk",

> +				      "pcie_1_pipe_clk";

>  			#clock-cells = <1>;

>  			#reset-cells = <1>;

>  			#power-domain-cells = <1>;

> @@ -2062,6 +2072,7 @@ pcie0_lane: lanes@1c06200 {

>  				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;

>  				clock-names = "pipe0";

>  

> +				#clock-cells = <0>;

>  				#phy-cells = <0>;

>  				clock-output-names = "pcie_0_pipe_clk";

>  			};

> @@ -2170,6 +2181,7 @@ pcie1_lane: lanes@1c06200 {

>  				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;

>  				clock-names = "pipe0";

>  

> +				#clock-cells = <0>;

>  				#phy-cells = <0>;

>  				clock-output-names = "pcie_1_pipe_clk";

>  			};

> -- 

> 2.30.2

>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 454f794af547..86f717d5bfb6 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1061,6 +1061,16 @@  soc: soc@0 {
 		gcc: clock-controller@100000 {
 			compatible = "qcom,gcc-sdm845";
 			reg = <0 0x00100000 0 0x1f0000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK_A>,
+				 <&sleep_clk>,
+				 <&pcie0_lane>,
+				 <&pcie1_lane>;
+			clock-names = "bi_tcxo",
+				      "bi_tcxo_ao",
+				      "sleep_clk",
+				      "pcie_0_pipe_clk",
+				      "pcie_1_pipe_clk";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
@@ -2062,6 +2072,7 @@  pcie0_lane: lanes@1c06200 {
 				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 				clock-names = "pipe0";
 
+				#clock-cells = <0>;
 				#phy-cells = <0>;
 				clock-output-names = "pcie_0_pipe_clk";
 			};
@@ -2170,6 +2181,7 @@  pcie1_lane: lanes@1c06200 {
 				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
 				clock-names = "pipe0";
 
+				#clock-cells = <0>;
 				#phy-cells = <0>;
 				clock-output-names = "pcie_1_pipe_clk";
 			};