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failure notice

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Wang Deqiang Dec. 9, 2014, 3:06 a.m. UTC 
This is a ping for

https://gcc.gnu.org/ml/gcc-patches/2014-10/msg01049.html
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Subject: failure notice
To: wang.deqiang@linaro.org


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Message-ID: <CADf_BoWznQfWGd_bjseOf4m+ccmP8_vDzECmuJLajFs1DGG7zQ@mail.gmail.com>
Subject: [testsuite patch] avoid test when compile options is conflict with
 default mthumb
From: Wang Deqiang <wang.deqiang@linaro.org>
To: gcc-patches@gcc.gnu.org
Content-Type: multipart/alternative; boundary=f46d043c7fac76a54a05052303b1

--f46d043c7fac76a54a05052303b1
Content-Type: text/plain; charset=UTF-8

When testing arm-linux-gnueabihf triple with configure options
--with-mode=thumb(that makes -mthumb option default).
some testcase is failed with error message "sorry, unimplemented: Thumb-1
hard-float VFP ABI".
I found gcc compiler show this error message when :
1. -mthumb is used with -march=armv6 (or armv5e) and -mcpu=xscale
2. the test source have function body.

And when -mthumb is the default option of compiler, the dg-skip-if
functions can not detect it,
There is no xscale check function in target-supports.exp in. so we need to
add it .
And there are only macros in the test program in
check_effective_target_arm* function . no function body, we need to add it
too.

Here is my patch:

2014-10-08  Wangdeqiang  <Wangdeqiang@linaro.org>
    * lib/target-supports.exp (check_effective_target_arm_xscale_ok): New
function.
    (check_effective_target_arm_arch_FUNC_ok): Add test function body.
    * gcc.target/arm/pr40887.c (dg-require-effective-target): add
arm_arch_v5te_ok check
    * gcc.target/arm/scd42-1.c (dg-require-effective-target): add
arm_xscale_ok check
    * gcc.target/arm/scd42-2.c : Likewise
    * gcc.target/arm/scd42-3.c : Likewise
    * gcc.target/arm/g2.c : Likewise
    * gcc.target/arm/xor-and.c (dg-require-effective-target): add
arm_arch_v6_ok check

--f46d043c7fac76a54a05052303b1
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: quoted-printable

<div dir=3D"ltr">When testing arm-linux-gnueabihf triple with configure opt=
ions --with-mode=3Dthumb(that makes -mthumb option default).<br>some testca=
se is failed with error message &quot;sorry, unimplemented: Thumb-1 hard-fl=
oat VFP ABI&quot;.<br>I found gcc compiler show this error message when :<b=
r>1. -mthumb is used with -march=3Darmv6 (or armv5e) and -mcpu=3Dxscale<br>=
2. the test source have function body.<br><br>And when -mthumb is the defau=
lt option of compiler, the dg-skip-if functions can not detect it,<br>There=
 is no xscale check function in target-supports.exp in. so we need to add i=
t .<br>And there are only macros in the test program in check_effective_tar=
get_arm* function . no function body, we need to add it too.<br><br>Here is=
 my patch:<br><br>2014-10-08=C2=A0 Wangdeqiang=C2=A0 &lt;<a href=3D"mailto:=
Wangdeqiang@linaro.org">Wangdeqiang@linaro.org</a>&gt;<br>=C2=A0=C2=A0=C2=
=A0 * lib/target-supports.exp (check_effective_target_arm_xscale_ok): New f=
unction.<br>=C2=A0=C2=A0=C2=A0 (check_effective_target_arm_arch_FUNC_ok): A=
dd test function body.<br>=C2=A0=C2=A0=C2=A0 * gcc.target/arm/pr40887.c (dg=
-require-effective-target): add arm_arch_v5te_ok check<br>=C2=A0=C2=A0=C2=
=A0 * gcc.target/arm/scd42-1.c (dg-require-effective-target): add arm_xscal=
e_ok check<br>=C2=A0=C2=A0=C2=A0 * gcc.target/arm/scd42-2.c : Likewise<br>=
=C2=A0=C2=A0=C2=A0 * gcc.target/arm/scd42-3.c : Likewise<br>=C2=A0=C2=A0=C2=
=A0 * gcc.target/arm/g2.c : Likewise<br>=C2=A0=C2=A0=C2=A0 * gcc.target/arm=
/xor-and.c (dg-require-effective-target): add arm_arch_v6_ok check<br><br>I=
ndex: gcc/testsuite/gcc.target/arm/pr40887.c<br>=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D<br>--- gcc/testsuite/gcc.target/arm/pr40887.c=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0 (revision 216115)<br>+++ gcc/testsuite/gcc.targ=
et/arm/pr40887.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (working copy)<br>@@ -1,6 +1=
,7 @@<br>=C2=A0/* { dg-skip-if &quot;need at least armv5&quot; { *-*-* } { =
&quot;-march=3Darmv[234]*&quot; } { &quot;&quot; } } */<br>=C2=A0/* { dg-op=
tions &quot;-O2 -march=3Darmv5te&quot; }=C2=A0 */<br>=C2=A0/* { dg-final { =
scan-assembler &quot;blx&quot; } } */<br>+/* { dg-require-effective-target =
arm_arch_v5te_ok } */<br>=C2=A0<br>=C2=A0int (*indirect_func)(int x);<br>=
=C2=A0<br>Index: gcc/testsuite/gcc.target/arm/scd42-2.c<br>=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D<br>--- gcc/testsuite/gcc.target/arm/sc=
d42-2.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (revision 216115)<br>+++ gcc/testsuit=
e/gcc.target/arm/scd42-2.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (working copy)<br>=
@@ -5,6 +5,7 @@<br>=C2=A0/* { dg-skip-if &quot;Test is specific to the Xsca=
le&quot; { arm*-*-* } { &quot;-mcpu=3D*&quot; } { &quot;-mcpu=3Dxscale&quot=
; } } */<br>=C2=A0/* { dg-skip-if &quot;Test is specific to ARM mode&quot; =
{ arm*-*-* } { &quot;-mthumb&quot; } { &quot;&quot; } } */<br>=C2=A0/* { dg=
-require-effective-target arm32 } */<br>+/* { dg-require-effective-target a=
rm_xscale_ok } */<br>=C2=A0<br>=C2=A0unsigned load2(void) __attribute__ ((n=
aked));<br>=C2=A0unsigned load2(void)<br>Index: gcc/testsuite/gcc.target/ar=
m/scd42-3.c<br>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D<br>--- g=
cc/testsuite/gcc.target/arm/scd42-3.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (revisi=
on 216115)<br>+++ gcc/testsuite/gcc.target/arm/scd42-3.c=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0 (working copy)<br>@@ -3,6 +3,7 @@<br>=C2=A0/* { dg-skip-if &qu=
ot;Test is specific to Xscale&quot; { arm*-*-* } { &quot;-march=3D*&quot; }=
 { &quot;-march=3Dxscale&quot; } } */<br>=C2=A0/* { dg-skip-if &quot;Test i=
s specific to Xscale&quot; { arm*-*-* } { &quot;-mcpu=3D*&quot; } { &quot;-=
mcpu=3Dxscale&quot; } } */<br>=C2=A0/* { dg-options &quot;-mcpu=3Dxscale -O=
&quot; } */<br>+/* { dg-require-effective-target arm_xscale_ok } */<br>=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <br>=C2=A0unsigned load=
4(void) __attribute__ ((naked));<br>=C2=A0unsigned load4(void)<br>Index: gc=
c/testsuite/gcc.target/arm/g2.c<br>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D<br>--- gcc/testsuite/gcc.target/arm/g2.c=C2=A0=C2=A0 (revision=
 216115)<br>+++ gcc/testsuite/gcc.target/arm/g2.c=C2=A0=C2=A0 (working copy=
)<br>@@ -5,6 +5,7 @@<br>=C2=A0/* { dg-skip-if &quot;Test is specific to the=
 Xscale&quot; { arm*-*-* } { &quot;-mcpu=3D*&quot; } { &quot;-mcpu=3Dxscale=
&quot; } } */<br>=C2=A0/* { dg-skip-if &quot;Test is specific to ARM mode&q=
uot; { arm*-*-* } { &quot;-mthumb&quot; } { &quot;&quot; } } */<br>=C2=A0/*=
 { dg-require-effective-target arm32 } */<br>+/* { dg-require-effective-tar=
get arm_xscale_ok } */<br>=C2=A0<br>=C2=A0/* Brett Gaines&#39; test case. *=
/<br>=C2=A0unsigned BCPL(unsigned) __attribute__ ((naked));<br>Index: gcc/t=
estsuite/gcc.target/arm/xor-and.c<br>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D<br>--- gcc/testsuite/gcc.target/arm/xor-and.c=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 (revision 216115)<br>+++ gcc/testsuite/gcc.target/arm/xo=
r-and.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (working copy)<br>@@ -1,6 +1,7 @@<br>=
=C2=A0/* { dg-do compile } */<br>=C2=A0/* { dg-options &quot;-O -march=3Dar=
mv6&quot; } */<br>=C2=A0/* { dg-prune-output &quot;switch .* conflicts with=
&quot; } */<br>+/* { dg-require-effective-target arm_arch_v6_ok } */<br>=C2=
=A0<br>=C2=A0unsigned short foo (unsigned short x)<br>=C2=A0{<br>Index: gcc=
/testsuite/gcc.target/arm/scd42-1.c<br>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D<br>--- gcc/testsuite/gcc.target/arm/scd42-1.c=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 (revision 216115)<br>+++ gcc/testsuite/gcc.target/arm/sc=
d42-1.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (working copy)<br>@@ -2,6 +2,7 @@<br>=
=C2=A0/* { dg-do compile } */<br>=C2=A0/* { dg-skip-if &quot;incompatible o=
ptions&quot; { arm*-*-* } { &quot;-march=3D*&quot; } { &quot;&quot; } } */<=
br>=C2=A0/* { dg-options &quot;-mcpu=3Dxscale -O&quot; } */<br>+/* { dg-req=
uire-effective-target arm_xscale_ok } */<br>=C2=A0<br>=C2=A0unsigned load1(=
void) __attribute__ ((naked));<br>=C2=A0unsigned load1(void)<br>Index: gcc/=
testsuite/lib/target-supports.exp<br>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D<br>--- gcc/testsuite/lib/target-supports.exp=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 (revision 216115)<br>+++ gcc/testsuite/lib/target-sup=
ports.exp=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (working copy)<br>@@ -2721,6 =
+2721,11 @@ foreach { armfunc armflag armdef } { v4<br>=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 #i=
f !defined (DEF)<br>=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 #error !DEF<br>=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 #endi=
f<br>+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0 int<br>+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 main (void)<br>+=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 {<br>+=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 return 0;<br>+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }<br>=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } &quot;FLAG&quot; ]<br>=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }<br>=C2=A0<br>@@ -2948,6 +2953,23 @@ =
proc check_effective_target_arm_hf_eabi<br>=C2=A0=C2=A0=C2=A0=C2=A0 }]<br>=
=C2=A0}<br>=C2=A0<br>+# Return 1 if this is an ARM target supporting -mcpu=
=3Dxscale.<br>+# Some multilibs may be incompatible with this option.<br>+p=
roc check_effective_target_arm_xscale_ok { } {<br>+=C2=A0=C2=A0=C2=A0 if { =
[check_effective_target_arm32] } {<br>+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 return [check_no_compiler_messages arm_xscale_ok object {<br>+=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 int dummy;<br>+=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 int<br>+=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 main (void)<br>+=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 {<br>+=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return 0=
;<br>+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 }<br>+=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } &quot;-mcpu=3Dxscale&quot;]<br=
>+=C2=A0=C2=A0=C2=A0 } else {<br>+=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 return 0<br>+=C2=A0=C2=A0=C2=A0 }<br>+}<br>+<br>=C2=A0# Return 1 if thi=
s is an ARM target supporting -mcpu=3Diwmmxt.<br>=C2=A0# Some multilibs may=
 be incompatible with this option.<br></div>

--f46d043c7fac76a54a05052303b1--
diff mbox

Patch

Index: gcc/testsuite/gcc.target/arm/pr40887.c
===================================================================
--- gcc/testsuite/gcc.target/arm/pr40887.c      (revision 216115)
+++ gcc/testsuite/gcc.target/arm/pr40887.c      (working copy)
@@ -1,6 +1,7 @@ 
 /* { dg-skip-if "need at least armv5" { *-*-* } { "-march=armv[234]*" } {
"" } } */
 /* { dg-options "-O2 -march=armv5te" }  */
 /* { dg-final { scan-assembler "blx" } } */
+/* { dg-require-effective-target arm_arch_v5te_ok } */

 int (*indirect_func)(int x);

Index: gcc/testsuite/gcc.target/arm/scd42-2.c
===================================================================
--- gcc/testsuite/gcc.target/arm/scd42-2.c      (revision 216115)
+++ gcc/testsuite/gcc.target/arm/scd42-2.c      (working copy)
@@ -5,6 +5,7 @@ 
 /* { dg-skip-if "Test is specific to the Xscale" { arm*-*-* } { "-mcpu=*"
} { "-mcpu=xscale" } } */
 /* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" }
{ "" } } */
 /* { dg-require-effective-target arm32 } */
+/* { dg-require-effective-target arm_xscale_ok } */

 unsigned load2(void) __attribute__ ((naked));
 unsigned load2(void)
Index: gcc/testsuite/gcc.target/arm/scd42-3.c
===================================================================
--- gcc/testsuite/gcc.target/arm/scd42-3.c      (revision 216115)
+++ gcc/testsuite/gcc.target/arm/scd42-3.c      (working copy)
@@ -3,6 +3,7 @@ 
 /* { dg-skip-if "Test is specific to Xscale" { arm*-*-* } { "-march=*" } {
"-march=xscale" } } */
 /* { dg-skip-if "Test is specific to Xscale" { arm*-*-* } { "-mcpu=*" } {
"-mcpu=xscale" } } */
 /* { dg-options "-mcpu=xscale -O" } */
+/* { dg-require-effective-target arm_xscale_ok } */

 unsigned load4(void) __attribute__ ((naked));
 unsigned load4(void)
Index: gcc/testsuite/gcc.target/arm/g2.c
===================================================================
--- gcc/testsuite/gcc.target/arm/g2.c   (revision 216115)
+++ gcc/testsuite/gcc.target/arm/g2.c   (working copy)
@@ -5,6 +5,7 @@ 
 /* { dg-skip-if "Test is specific to the Xscale" { arm*-*-* } { "-mcpu=*"
} { "-mcpu=xscale" } } */
 /* { dg-skip-if "Test is specific to ARM mode" { arm*-*-* } { "-mthumb" }
{ "" } } */
 /* { dg-require-effective-target arm32 } */
+/* { dg-require-effective-target arm_xscale_ok } */

 /* Brett Gaines' test case. */
 unsigned BCPL(unsigned) __attribute__ ((naked));
Index: gcc/testsuite/gcc.target/arm/xor-and.c
===================================================================
--- gcc/testsuite/gcc.target/arm/xor-and.c      (revision 216115)
+++ gcc/testsuite/gcc.target/arm/xor-and.c      (working copy)
@@ -1,6 +1,7 @@ 
 /* { dg-do compile } */
 /* { dg-options "-O -march=armv6" } */
 /* { dg-prune-output "switch .* conflicts with" } */
+/* { dg-require-effective-target arm_arch_v6_ok } */

 unsigned short foo (unsigned short x)
 {
Index: gcc/testsuite/gcc.target/arm/scd42-1.c
===================================================================
--- gcc/testsuite/gcc.target/arm/scd42-1.c      (revision 216115)
+++ gcc/testsuite/gcc.target/arm/scd42-1.c      (working copy)
@@ -2,6 +2,7 @@ 
 /* { dg-do compile } */
 /* { dg-skip-if "incompatible options" { arm*-*-* } { "-march=*" } { "" }
} */
 /* { dg-options "-mcpu=xscale -O" } */
+/* { dg-require-effective-target arm_xscale_ok } */

 unsigned load1(void) __attribute__ ((naked));
 unsigned load1(void)
Index: gcc/testsuite/lib/target-supports.exp
===================================================================
--- gcc/testsuite/lib/target-supports.exp       (revision 216115)
+++ gcc/testsuite/lib/target-supports.exp       (working copy)
@@ -2721,6 +2721,11 @@  foreach { armfunc armflag armdef } { v4
                #if !defined (DEF)
                #error !DEF
                #endif
+               int
+               main (void)
+               {
+                  return 0;
+               }
            } "FLAG" ]
        }

@@ -2948,6 +2953,23 @@  proc check_effective_target_arm_hf_eabi
     }]
 }

+# Return 1 if this is an ARM target supporting -mcpu=xscale.
+# Some multilibs may be incompatible with this option.
+proc check_effective_target_arm_xscale_ok { } {
+    if { [check_effective_target_arm32] } {
+        return [check_no_compiler_messages arm_xscale_ok object {
+           int dummy;
+           int
+           main (void)
+           {
+              return 0;
+           }
+        } "-mcpu=xscale"]
+    } else {
+        return 0
+    }
+}
+
 # Return 1 if this is an ARM target supporting -mcpu=iwmmxt.
 # Some multilibs may be incompatible with this option.